Cross Reference: /src/sys/arch/powerpc/booke/dev/pq3etsec.c

Lines Matching defs:etsec_write
465 etsec_write(struct pq3etsec_softc *sc, bus_size_t off, uint32_t data)
642 	etsec_write(sc, IMASK, 0);
725 	etsec_write(sc, ATTR, ATTR_DEFAULT);
726 	etsec_write(sc, ATTRELI, ATTRELI_DEFAULT);
971 	etsec_write(sc, MAXFRM, sc->sc_maxfrm);
972 	etsec_write(sc, MACSTNADDR1, (uint32_t)(macstnaddr >> 32));
973 	etsec_write(sc, MACSTNADDR2, (uint32_t)(macstnaddr >>  0));
974 	etsec_write(sc, MACCFG1, sc->sc_maccfg1);
975 	etsec_write(sc, MACCFG2, sc->sc_maccfg2);
976 	etsec_write(sc, ECNTRL, sc->sc_ecntrl);
982 	etsec_write(sc, MRBLR, MCLBYTES);
986 	etsec_write(sc, DMACTRL, sc->sc_dmactrl);
989 	etsec_write(sc, TQUEUE, TQUEUE_EN0);
992 	etsec_write(sc, TCTRL, sc->sc_tctrl);	/* for TOE stuff */
995 	etsec_write(sc, RQUEUE, RQUEUE_EN0 | RQUEUE_EX0);
999 	etsec_write(sc, RCTRL, sc->sc_rctrl);
1005 	etsec_write(sc, TSTAT, TSTAT_THLT | TSTAT_TXF);
1008 	etsec_write(sc, RSTAT, RSTAT_QHLT | RSTAT_RXF);
1012 	etsec_write(sc, DMACTRL, sc->sc_dmactrl);
1015 	etsec_write(sc, MACCFG1, sc->sc_maccfg1 | MACCFG1_TX_EN|MACCFG1_RX_EN);
1016 	etsec_write(sc, MACCFG1, sc->sc_maccfg1 | MACCFG1_TX_EN|MACCFG1_RX_EN);
1020 	etsec_write(sc, IMASK, sc->sc_imask);
1047 	etsec_write(sc, IMASK, sc->sc_imask & ~imask_gsc_mask);
1048 	etsec_write(sc, IEVENT, imask_gsc_mask);
1049 	etsec_write(sc, DMACTRL, sc->sc_dmactrl);
1055 		etsec_write(sc, IMASK, sc->sc_imask | imask_gsc_mask);
1078 	etsec_write(sc, MACCFG1, MACCFG1_SOFT_RESET);
1079 	etsec_write(sc, MACCFG1, 0);
1080 	etsec_write(sc, IMASK, 0);
1081 	etsec_write(sc, IEVENT, ~0);
1088 		etsec_write(sc, TBIPA, 0x1f);
1091 	etsec_write(sc, MIIMCFG, MIIMCFG_RESET);
1092 	etsec_write(sc, MIIMCFG, miimcfg);
1169 		etsec_write(sc, IGADDR(i), sc->sc_gaddr[i]);
1170 		etsec_write(sc, GADDR(i), sc->sc_gaddr[i+8]);
1180 		etsec_write(sc, MACnADDR1(i), (uint32_t)(macaddr >> 32));
1181 		etsec_write(sc, MACnADDR2(i), (uint32_t)(macaddr >>  0));
1532 		etsec_write(sc, RSTAT, RSTAT_QHLT & rxq->rxq_qmask);
1620 	etsec_write(sc, RSTAT, RSTAT_RXF & rxq->rxq_qmask);
1783 	etsec_write(sc, rxq->rxq_reg_rbase, rxq->rxq_descmap->dm_segs->ds_addr);
2012 	etsec_write(sc, TSTAT, txq->txq_qmask & TSTAT_THLT);	/* W1C */
2170 	etsec_write(sc, TSTAT, TSTAT_TXF & txq->txq_qmask);
2326 	etsec_write(sc, txq->txq_reg_tbase, txq->txq_descmap->dm_segs->ds_addr);
2356 		etsec_write(sc, TSTAT, TSTAT_THLT & txq->txq_qmask);
2375 	etsec_write(sc, IEVENT, ievent);	/* write 1 to clear */
2389 	etsec_write(sc, IMASK, sc->sc_imask);
2408 	etsec_write(sc, IEVENT, ievent);	/* write 1 to clear */
2420 	etsec_write(sc, IMASK, sc->sc_imask);
2440 		etsec_write(sc, IEVENT, ievent);	/* write 1 to clear */
2456 			etsec_write(sc, IMASK, sc->sc_imask);
2461 			etsec_write(sc, IMASK, sc->sc_imask);
2467 			etsec_write(sc, IMASK, sc->sc_imask);
2483 			etsec_write(sc, IMASK, sc->sc_imask);
2550 		etsec_write(sc, IMASK, sc->sc_imask);
2600 	etsec_write(sc, RXIC, reg);
2617 	etsec_write(sc, TXIC, reg);
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