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Lines Matching refs:outw

178 			outw(VGA_SR_PORT, 0x0612); /* unlock ext regs */
179 			outw(VGA_SR_PORT, 0x0700); /* reset ext sequence mode */
184 			outw(VGA_GR_PORT, 0x0f05); /* unlock registers */
185 			outw(VGA_SR_PORT, 0x0648);
186 			outw(VGA_CR_PORT, 0x2985);
187 			outw(VGA_CR_PORT, 0x34a6);
190 			outw(VGA_SR_PORT, 0x1400);
199 				outw(VGA_CR_PORT, 0x0250);
200 				outw(VGA_CR_PORT, 0x07ba);
201 				outw(VGA_CR_PORT, 0x0900);
202 				outw(VGA_CR_PORT, 0x15e7);
203 				outw(VGA_CR_PORT, 0x2a95);
205 			outw(VGA_CR_PORT, 0x34a0);
217 			outw(VGA_SR_PORT, 0x0120); /* disable video */
222 			outw(VGA_SR_PORT, 0x0100); /* re-enable video */
300 	outw(0x3C4, 0x0001);	/* reset sequencer */
301 	outw(0x3C4, 0x0204);	/* write to plane 2 */
302 	outw(0x3C4, 0x0406);	/* enable plane graphics */
303 	outw(0x3C4, 0x0003);	/* reset sequencer */
304 	outw(0x3CE, 0x0402);	/* read plane 2 */
305 	outw(0x3CE, 0x0500);	/* write mode 0, read mode 0 */
306 	outw(0x3CE, 0x0605);	/* set graphics mode */
321 	outw(VGA_CR_PORT, 0x3848);
322 	outw(VGA_CR_PORT, 0x39a5);
371 		outw(VGA_SR_PORT, 0x0806);
372 		outw(VGA_SR_PORT, 0x1041);
373 		outw(VGA_SR_PORT, 0x1128);
374 		outw(VGA_CR_PORT, 0x4000);
375 		outw(VGA_CR_PORT, 0x3100);
376 		outw(VGA_CR_PORT, 0x3a05);
377 		outw(VGA_CR_PORT, 0x6688);
378 		outw(VGA_CR_PORT, 0x5800); /* disable linear addressing */
379 		outw(VGA_CR_PORT, 0x4500); /* disable H/W cursor */
380 		outw(VGA_SR_PORT, 0x5410); /* enable auto-centering */
381 		outw(VGA_SR_PORT, 0x561f);
382 		outw(VGA_SR_PORT, 0x1b80); /* lock DCLK selection */
383 		outw(VGA_CR_PORT, 0x3900); /* lock S3 registers */
384 		outw(VGA_CR_PORT, 0x3800);