Lines Matching refs:SUNXI_CCU_GATE
341 SUNXI_CCU_GATE(D1_CLK_BUS_DE, "bus-de", "psi",
344 SUNXI_CCU_GATE(D1_CLK_BUS_DI, "bus-di", "psi",
347 SUNXI_CCU_GATE(D1_CLK_BUS_G2D, "bus-g2d", "psi",
350 SUNXI_CCU_GATE(D1_CLK_BUS_CE, "bus-ce", "psi",
353 SUNXI_CCU_GATE(D1_CLK_BUS_VE, "bus-ve", "psi",
356 SUNXI_CCU_GATE(D1_CLK_BUS_DMA, "bus-dma", "psi",
359 SUNXI_CCU_GATE(D1_CLK_BUS_MSGBOX0, "bus-msgbox0", "psi",
361 SUNXI_CCU_GATE(D1_CLK_BUS_MSGBOX1, "bus-msgbox1", "psi",
363 SUNXI_CCU_GATE(D1_CLK_BUS_MSGBOX2, "bus-msgbox2", "psi",
366 SUNXI_CCU_GATE(D1_CLK_BUS_SPINLOCK, "bus-spinlock", "psi",
369 SUNXI_CCU_GATE(D1_CLK_BUS_HSTIMER, "bus-hstimer", "psi",
372 SUNXI_CCU_GATE(D1_CLK_AVS, "avs", "hosc",
375 SUNXI_CCU_GATE(D1_CLK_BUS_DBGSYS, "bus-dbgsys", "psi",
378 SUNXI_CCU_GATE(D1_CLK_BUS_PWM, "bus-pwm", "apb0",
381 SUNXI_CCU_GATE(D1_CLK_BUS_IOMMU, "bus-iommu", "apb0",
384 SUNXI_CCU_GATE(D1_CLK_MBUS_DMA, "mbus-dma", "mbus",
386 SUNXI_CCU_GATE(D1_CLK_MBUS_VE, "mbus-ve", "mbus",
388 SUNXI_CCU_GATE(D1_CLK_MBUS_CE, "mbus-ce", "mbus",
390 SUNXI_CCU_GATE(D1_CLK_MBUS_TVIN, "mbus-tvin", "mbus",
392 SUNXI_CCU_GATE(D1_CLK_MBUS_CSI, "mbus-csi", "mbus",
394 SUNXI_CCU_GATE(D1_CLK_MBUS_G2D, "mbus-g2d", "mbus",
396 SUNXI_CCU_GATE(D1_CLK_MBUS_RISCV, "mbus-riscv", "mbus",
399 SUNXI_CCU_GATE(D1_CLK_BUS_DRAM, "bus-dram", "psi",
402 SUNXI_CCU_GATE(D1_CLK_BUS_MMC0, "bus-mmc0", "psi",
404 SUNXI_CCU_GATE(D1_CLK_BUS_MMC1, "bus-mmc1", "psi",
406 SUNXI_CCU_GATE(D1_CLK_BUS_MMC2, "bus-mmc2", "psi",
409 SUNXI_CCU_GATE(D1_CLK_BUS_UART0, "bus-uart0", "apb1",
411 SUNXI_CCU_GATE(D1_CLK_BUS_UART1, "bus-uart1", "apb1",
413 SUNXI_CCU_GATE(D1_CLK_BUS_UART2, "bus-uart2", "apb1",
415 SUNXI_CCU_GATE(D1_CLK_BUS_UART3, "bus-uart3", "apb1",
417 SUNXI_CCU_GATE(D1_CLK_BUS_UART4, "bus-uart4", "apb1",
419 SUNXI_CCU_GATE(D1_CLK_BUS_UART5, "bus-uart5", "apb1",
422 SUNXI_CCU_GATE(D1_CLK_BUS_I2C0, "bus-i2c0", "apb1",
424 SUNXI_CCU_GATE(D1_CLK_BUS_I2C1, "bus-i2c1", "apb1",
426 SUNXI_CCU_GATE(D1_CLK_BUS_I2C2, "bus-i2c2", "apb1",
428 SUNXI_CCU_GATE(D1_CLK_BUS_I2C3, "bus-i2c3", "apb1",
431 SUNXI_CCU_GATE(D1_CLK_BUS_SPI0, "bus-spi0", "psi",
433 SUNXI_CCU_GATE(D1_CLK_BUS_SPI1, "bus-spi1", "psi",
436 SUNXI_CCU_GATE(D1_CLK_BUS_EMAC, "bus-emac", "psi",
439 SUNXI_CCU_GATE(D1_CLK_BUS_IRTX, "bus-irtx", "apb0",
442 SUNXI_CCU_GATE(D1_CLK_BUS_GPADC, "bus-gpadc", "apb0",
445 SUNXI_CCU_GATE(D1_CLK_BUS_THS, "bus-ths", "apb0",
448 SUNXI_CCU_GATE(D1_CLK_BUS_I2S0, "bus-i2s0", "apb0",
450 SUNXI_CCU_GATE(D1_CLK_BUS_I2S1, "bus-i2s1", "apb0",
452 SUNXI_CCU_GATE(D1_CLK_BUS_I2S2, "bus-i2s2", "apb0",
455 SUNXI_CCU_GATE(D1_CLK_BUS_SPDIF, "bus-spdif", "apb0",
458 SUNXI_CCU_GATE(D1_CLK_BUS_DMIC, "bus-dmic", "apb0",
461 SUNXI_CCU_GATE(D1_CLK_BUS_AUDIO, "bus-audio", "apb0",
464 SUNXI_CCU_GATE(D1_CLK_BUS_OHCI0, "bus-ohci0", "psi",
466 SUNXI_CCU_GATE(D1_CLK_BUS_OHCI1, "bus-ohci1", "psi",
468 SUNXI_CCU_GATE(D1_CLK_BUS_EHCI0, "bus-ehci0", "psi",
470 SUNXI_CCU_GATE(D1_CLK_BUS_EHCI1, "bus-ehci1", "psi",
472 SUNXI_CCU_GATE(D1_CLK_BUS_OTG, "bus-otg", "psi",
475 SUNXI_CCU_GATE(D1_CLK_BUS_LRADC, "bus-lradc", "apb0",
478 SUNXI_CCU_GATE(D1_CLK_BUS_DPSS_TOP, "bus-dpss-top", "psi",
481 SUNXI_CCU_GATE(D1_CLK_BUS_HDMI, "bus-hdmi", "psi",
484 SUNXI_CCU_GATE(D1_CLK_BUS_DSI, "bus-dsi", "psi",
487 SUNXI_CCU_GATE(D1_CLK_BUS_TCONLCD, "bus-tconlcd", "psi",
490 SUNXI_CCU_GATE(D1_CLK_BUS_TCONTV, "bus-tcontv", "psi",
493 SUNXI_CCU_GATE(D1_CLK_BUS_TVE_TOP, "bus-tve-top", "psi",
495 SUNXI_CCU_GATE(D1_CLK_BUS_TVE, "bus-tve", "psi",
498 SUNXI_CCU_GATE(D1_CLK_BUS_TVD_TOP, "bus-tvd-top", "psi",
500 SUNXI_CCU_GATE(D1_CLK_BUS_TVD, "bus-tvd", "psi",
503 SUNXI_CCU_GATE(D1_CLK_BUS_LEDC, "bus-ledc", "psi",
506 SUNXI_CCU_GATE
509 SUNXI_CCU_GATE(D1_CLK_BUS_TPADC, "bus-tpadc", "apb0",
512 SUNXI_CCU_GATE(D1_CLK_BUS_DSP_CFG, "bus-dsp-cfg", "psi",
515 SUNXI_CCU_GATE(D1_CLK_BUS_RISCV_CFG, "bus-riscv-cfg", "psi",
Indexes created Thu Oct 23 18:09:57 GMT 2025