Lines Matching refs:sunxi_ccu_reset
111 static struct sunxi_ccu_reset sun20i_d1_ccu_resets[] = {
112 SUNXI_CCU_RESET(D1_RST_MBUS, MBUS_CLK_REG, 30),
114 SUNXI_CCU_RESET(D1_RST_BUS_DE, DE_BGR_REG, 16),
116 SUNXI_CCU_RESET(D1_RST_BUS_DI, DI_BGR_REG, 16),
118 SUNXI_CCU_RESET(D1_RST_BUS_G2D, G2D_BGR_REG, 16),
120 SUNXI_CCU_RESET(D1_RST_BUS_CE, CE_BGR_REG, 16),
122 SUNXI_CCU_RESET(D1_RST_BUS_VE, VE_BGR_REG, 16),
124 SUNXI_CCU_RESET(D1_RST_BUS_DMA, DMA_BGR_REG, 16),
126 SUNXI_CCU_RESET(D1_RST_BUS_MSGBOX0, MSGBOX_BGR_REG, 16),
127 SUNXI_CCU_RESET(D1_RST_BUS_MSGBOX1, MSGBOX_BGR_REG, 17),
128 SUNXI_CCU_RESET(D1_RST_BUS_MSGBOX2, MSGBOX_BGR_REG, 18),
130 SUNXI_CCU_RESET(D1_RST_BUS_SPINLOCK, SPINLOCK_BGR_REG, 16),
132 SUNXI_CCU_RESET(D1_RST_BUS_HSTIMER, HSTIMER_BGR_REG, 16),
134 SUNXI_CCU_RESET(D1_RST_BUS_DBGSYS, DBGSYS_BGR_REG, 16),
136 SUNXI_CCU_RESET(D1_RST_BUS_PWM, PWM_BGR_REG, 16),
138 SUNXI_CCU_RESET(D1_RST_BUS_DRAM, DRAM_BGR_REG, 16),
140 SUNXI_CCU_RESET(D1_RST_BUS_MMC0, SMHC_BGR_REG, 16),
141 SUNXI_CCU_RESET(D1_RST_BUS_MMC1, SMHC_BGR_REG, 17),
142 SUNXI_CCU_RESET(D1_RST_BUS_MMC2, SMHC_BGR_REG, 18),
144 SUNXI_CCU_RESET(D1_RST_BUS_UART0, UART_BGR_REG, 16),
145 SUNXI_CCU_RESET(D1_RST_BUS_UART1, UART_BGR_REG, 17),
146 SUNXI_CCU_RESET(D1_RST_BUS_UART2, UART_BGR_REG, 18),
147 SUNXI_CCU_RESET(D1_RST_BUS_UART3, UART_BGR_REG, 19),
148 SUNXI_CCU_RESET(D1_RST_BUS_UART4, UART_BGR_REG, 20),
149 SUNXI_CCU_RESET(D1_RST_BUS_UART5, UART_BGR_REG, 21),
151 SUNXI_CCU_RESET(D1_RST_BUS_I2C0, TWI_BGR_REG, 16),
152 SUNXI_CCU_RESET(D1_RST_BUS_I2C1, TWI_BGR_REG, 17),
153 SUNXI_CCU_RESET(D1_RST_BUS_I2C2, TWI_BGR_REG, 18),
154 SUNXI_CCU_RESET(D1_RST_BUS_I2C3, TWI_BGR_REG, 19),
156 SUNXI_CCU_RESET(D1_RST_BUS_SPI0, SPI_BGR_REG, 16),
157 SUNXI_CCU_RESET(D1_RST_BUS_SPI1, SPI_BGR_REG, 17),
159 SUNXI_CCU_RESET(D1_RST_BUS_EMAC, EMAC_BGR_REG, 16),
161 SUNXI_CCU_RESET(D1_RST_BUS_IRTX, IRTX_BGR_REG, 16),
163 SUNXI_CCU_RESET(D1_RST_BUS_GPADC, GPADC_BGR_REG, 16),
165 SUNXI_CCU_RESET(D1_RST_BUS_THS, THS_BGR_REG, 16),
167 SUNXI_CCU_RESET(D1_RST_BUS_I2S0, I2S_BGR_REG, 16),
168 SUNXI_CCU_RESET(D1_RST_BUS_I2S1, I2S_BGR_REG, 17),
169 SUNXI_CCU_RESET(D1_RST_BUS_I2S2, I2S_BGR_REG, 18),
171 SUNXI_CCU_RESET(D1_RST_BUS_SPDIF, OWA_BGR_REG, 16),
173 SUNXI_CCU_RESET(D1_RST_BUS_DMIC, DMIC_BGR_REG, 16),
175 SUNXI_CCU_RESET(D1_RST_BUS_AUDIO, AUDIO_CODEC_BGR_REG, 16),
177 SUNXI_CCU_RESET(D1_RST_USB_PHY0, USB0_CLK_REG, 30),
179 SUNXI_CCU_RESET(D1_RST_USB_PHY1, USB1_CLK_REG, 30),
181 SUNXI_CCU_RESET(D1_RST_BUS_OHCI0, USB_BGR_REG, 16),
182 SUNXI_CCU_RESET(D1_RST_BUS_OHCI1, USB_BGR_REG, 17),
183 SUNXI_CCU_RESET(D1_RST_BUS_EHCI0, USB_BGR_REG, 20),
184 SUNXI_CCU_RESET(D1_RST_BUS_EHCI1, USB_BGR_REG, 21),
185 SUNXI_CCU_RESET(D1_RST_BUS_OTG, USB_BGR_REG, 24),
187 SUNXI_CCU_RESET(D1_RST_BUS_LRADC, LRADC_BGR_REG, 16),
189 SUNXI_CCU_RESET(D1_RST_BUS_DPSS_TOP, DPSS_TOP_BGR_REG, 16),
191 SUNXI_CCU_RESET(D1_RST_BUS_HDMI_SUB, HDMI_BGR_REG, 17),
192 SUNXI_CCU_RESET(D1_RST_BUS_HDMI_MAIN, HDMI_BGR_REG, 16),
194 SUNXI_CCU_RESET(D1_RST_BUS_DSI, DSI_BGR_REG, 16),
196 SUNXI_CCU_RESET(D1_RST_BUS_TCONLCD, TCONLCD_BGR_REG, 16),
198 SUNXI_CCU_RESET(D1_RST_BUS_TCONTV, TCONTV_BGR_REG, 16),
200 SUNXI_CCU_RESET(D1_RST_BUS_LVDS, LVDS_BGR_REG, 16),
202 SUNXI_CCU_RESET(D1_RST_BUS_TVE_TOP, TVE_BGR_REG, 16),
203 SUNXI_CCU_RESET(D1_RST_BUS_TVE, TVE_BGR_REG, 17),
205 SUNXI_CCU_RESET(D1_RST_BUS_TVD_TOP, TVD_BGR_REG, 16),
206 SUNXI_CCU_RESET(D1_RST_BUS_TVD, TVD_BGR_REG, 17),
208 SUNXI_CCU_RESET(D1_RST_BUS_LEDC, LEDC_BGR_REG, 16),
210 SUNXI_CCU_RESET(D1_RST_BUS_CSI, CSI_BGR_REG, 16),
212 SUNXI_CCU_RESET(D1_RST_BUS_TPADC, TPADC_BGR_REG, 16),
214 SUNXI_CCU_RESET(D1_RST_BUS_DSP, DSP_BGR_REG, 16),
215 SUNXI_CCU_RESET(D1_RST_BUS_DSP_CFG, DSP_BGR_REG, 17),
216 SUNXI_CCU_RESET(D1_RST_BUS_DSP_DBG, DSP_BGR_REG, 18),
218 SUNXI_CCU_RESET(D1_RST_BUS_RISCV_CFG, RISCV_CFG_BGR_REG, 16),
Indexes created Wed Oct 22 13:09:56 GMT 2025