Lines Matching refs:CSR_WRITE_4
50 #define CSR_WRITE_4(l, r, v) out32rb((l)->csr+(r), (v))
229 CSR_WRITE_4(l, SK_RAMCTL, 2); /* enable RAM interface */
252 CSR_WRITE_4(l, SK_RXMF1_CTRL_TEST, RFCTL_OPERATION_ON);
254 CSR_WRITE_4(l, SK_TXMF1_CTRL_TEST, TFCTL_OPERATION_ON);
274 CSR_WRITE_4(l, SK_RXRB1_CTLTST, RBCTL_UNRESET);
275 CSR_WRITE_4(l, SK_RXRB1_START, 0);
276 CSR_WRITE_4(l, SK_RXRB1_WR_PTR, 0);
277 CSR_WRITE_4(l, SK_RXRB1_RD_PTR, 0);
278 CSR_WRITE_4(l, SK_RXRB1_END, 0xfff);
279 CSR_WRITE_4(l, SK_RXRB1_CTLTST, RBCTL_ON);
280 CSR_WRITE_4(l, SK_TXRBS1_CTLTST, RBCTL_UNRESET);
281 CSR_WRITE_4(l, SK_TXRBS1_CTLTST, RBCTL_STORENFWD_ON);
282 CSR_WRITE_4(l, SK_TXRBS1_START, 0x1000);
283 CSR_WRITE_4(l, SK_TXRBS1_WR_PTR, 0x1000);
284 CSR_WRITE_4(l, SK_TXRBS1_RD_PTR, 0x1000);
285 CSR_WRITE_4(l, SK_TXRBS1_END, 0x1fff);
286 CSR_WRITE_4(l, SK_TXRBS1_CTLTST, RBCTL_ON);
303 CSR_WRITE_4(l, SK_RXQ1_BMU_CSR,
308 CSR_WRITE_4(l, SK_RXQ1_CURADDR_LO, VTOPHYS(rxd));
309 CSR_WRITE_4(l, SK_RXQ1_CURADDR_HI, 0);
311 CSR_WRITE_4(l, SK_TXQS1_BMU_CSR,
316 CSR_WRITE_4(l, SK_TXQS1_CURADDR_LO, VTOPHYS(txd));
317 CSR_WRITE_4(l, SK_TXQS1_CURADDR_HI, 0);
319 CSR_WRITE_4(l, SK_IMR, 0);
320 CSR_WRITE_4(l, SK_RXQ1_BMU_CSR, RXBMU_RX_START);
340 CSR_WRITE_4(l, SK_BMU_TXS_CSR0, TXBMU_TX_START);
464 CSR_WRITE_4(l, SK_GPIO, (val | 0x2000000) & ~0x200);
467 CSR_WRITE_4(l, SK_GPHY_CTRL, GPHY_RESET_SET);
468 CSR_WRITE_4(l, SK_GMAC_CTRL, GMAC_RESET_SET);
470 CSR_WRITE_4(l, SK_GMAC_CTRL, GMAC_RESET_CLEAR);
471 CSR_WRITE_4(l, SK_GMAC_CTRL, GMAC_RESET_SET);
476 CSR_WRITE_4(l, SK_GPHY_CTRL, val | GPHY_RESET_SET);
478 CSR_WRITE_4(l, SK_GPHY_CTRL, val | GPHY_RESET_CLEAR);
479 CSR_WRITE_4(l, SK_GMAC_CTRL, GMAC_LOOP_OFF | GMAC_PAUSE_ON |
Indexes created Sun Oct 19 01:09:53 GMT 2025