Cross Reference: /src/sys/arch/sgimips/hpc/if

Lines Matching defs:sq_hpc_write
132 #define sq_hpc_write(sc, off, val) \
439 		sq_hpc_write(sc, HPC3_ENETR_PIOCFG, pioreg);
440 		sq_hpc_write(sc, HPC3_ENETR_DMACFG, dmareg);
444 	sq_hpc_write(sc, sc->hpc_regs->enetr_ndbp, SQ_CDRXADDR(sc, 0));
447 	sq_hpc_write(sc, sc->hpc_regs->enetr_ctl,
455 		sq_hpc_write(sc, HPC1_ENET_INTDELAY, HPC1_ENET_INTDELAY_OFF);
777 			sq_hpc_write(sc, HPC3_ENETX_NDBP, SQ_CDTXADDR(sc,
781 			sq_hpc_write(sc, HPC3_ENETX_CTL, HPC3_ENETX_CTL_ACTIVE);
794 				sq_hpc_write(sc, HPC1_ENETX_NDBP,
796 				sq_hpc_write(sc, HPC1_ENETX_CFXBP,
798 				sq_hpc_write(sc, HPC1_ENETX_CBP,
802 				sq_hpc_write(sc, HPC1_ENETX_CTL,
901 		sq_hpc_write(sc, sc->hpc_regs->enetr_reset, (stat | 2));
1043 		sq_hpc_write(sc, sc->hpc_regs->enetr_ndbp,
1047 		sq_hpc_write(sc, sc->hpc_regs->enetr_ctl,
1166 		sq_hpc_write(sc, HPC1_ENETX_CFXBP, reclaimto);
1167 		sq_hpc_write(sc, HPC1_ENETX_CBP, reclaimto);
1170 		sq_hpc_write(sc, HPC1_ENETX_CTL, HPC1_ENETX_CTL_ACTIVE);
1217 				sq_hpc_write(sc, HPC3_ENETX_NDBP,
1221 				sq_hpc_write(sc, HPC3_ENETX_CTL,
1256 	sq_hpc_write(sc, sc->hpc_regs->enetr_ctl, 0);
1257 	sq_hpc_write(sc, sc->hpc_regs->enetx_ctl, 0);
1259 	sq_hpc_write(sc, sc->hpc_regs->enetr_reset, 3);
1261 	sq_hpc_write(sc, sc->hpc_regs->enetr_reset, 0);
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