Lines Matching refs:csr
104 uint8_t csr;
127 GET_SBIC_csr(sc, csr);
128 __USE(csr);
165 uint8_t csr, asr;
172 if ((csr = wd33c93_selectbus(sc, cbuf, clen, buf, lenp)) == 0)
182 i = wd33c93_nextstate(sc, cbuf, clen, buf, lenp, csr, asr);
191 GET_SBIC_csr(sc, csr);
216 * Returns the current CSR following selection and optionally MSG out phase.
217 * i.e. the returned CSR *should* indicate CMD phase...
224 uint8_t asr, csr, id, lun, target;
260 GET_SBIC_csr(sc, csr);
263 if (csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY) {
267 wd33c93_nextstate(sc, cbuf, clen, buf, lenp, csr, asr);
271 if (csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN) {
274 } while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) &&
275 csr != (SBIC_CSR_MIS_2 | CMD_PHASE) &&
276 csr != SBIC_CSR_SEL_TIMEO);
279 if (csr == SBIC_CSR_SEL_TIMEO) {
309 if (csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE)) {
334 GET_SBIC_csr(sc, csr);
336 return csr;
362 uint8_t *buf, size_t *lenp, uint8_t csr, uint8_t asr)
367 switch (csr) {
406 if (SBIC_PHASE(csr) == DATA_IN_PHASE){
453 if (csr == SBIC_CSR_RSLT_IFY)
531 uint8_t asr, csr;
540 GET_SBIC_csr(sc, csr);
544 (void)wd33c93_nextstate(sc, cbuf, clen, buf, lenp, csr, asr);
550 GET_SBIC_csr(sc, csr);
601 * this leaves with one csr to be read
614 uint8_t phase, csr;
625 GET_SBIC_csr(sc, csr);
626 } while ((csr != SBIC_CSR_DISC) &&
627 (csr != SBIC_CSR_DISC_1) &&
628 (csr != SBIC_CSR_S_XFERRED));
645 uint8_t csr, asr;
648 GET_SBIC_csr(sc, csr);
686 GET_SBIC_csr(sc, csr);
687 csr != SBIC_CSR_DISC) &&
688 (csr != SBIC_CSR_DISC_1) &&
689 (csr != SBIC_CSR_CMD_INVALID));
723 uint8_t asr, csr = 0;
733 GET_SBIC_csr(sc, csr);
734 (void)wd33c93_nextstate(sc, cbuf, clen, buf, lenp, csr,
769 uint8_t asr, csr, *msg;
774 GET_SBIC_selid(sc, csr);
775 SET_SBIC_selid(sc, csr | SBIC_SID_FROM_SCSI);
794 GET_SBIC_csr(sc, csr);
807 GET_SBIC_csr(sc, csr);
817 /* Should still have one CSR to read */