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Lines Matching refs:SH_

103 	_reg_bclr_1(SH_(TSTR), TSTR_STR##x);				\
104 	_reg_write_4(SH_(TCNT ## x), 0xffffffff);			\
105 	_reg_bset_1(SH_(TSTR), TSTR_STR##x);				\
109 	(0xffffffff - _reg_read_4(SH_(TCNT ## x)))
119 	_reg_write_2(SH_(TCR0), 0);
120 	_reg_write_2(SH_(TCR1), 0);
121 	_reg_write_2(SH_(TCR2), 0);
124 	_reg_write_1(SH_(RCR1), 0);
127 	_reg_write_1(SH_(TSTR), 0);
134 		_reg_write_2(SH_(TCR0), TCR_TPSC_P16);
138 		_reg_write_2(SH_(TCR0),
143 		_reg_bset_1(SH_(RCR2), SH_RCR2_ENABLE);
168 		_reg_write_2(SH_(TCR1), TCR_TPSC_P4);
183 	_reg_write_1(SH_(TSTR), 0);
213 	return 0xffffffff - _reg_read_4(SH_(TCNT2));
243 	_reg_bclr_1(SH_(TSTR), TSTR_STR0);
247 		_reg_write_2(SH_(TCR0), TCR_UNIE | TCR_TPSC_P16);
250 		_reg_write_2(SH_(TCR0), TCR_UNIE |
255 	_reg_write_4(SH_(TCOR0), sh_clock.hz_cnt);
256 	_reg_write_4(SH_(TCNT0), sh_clock.hz_cnt);
262 	_reg_bset_1(SH_(TSTR), TSTR_STR0);
267 	_reg_write_2(SH_(TCR1), TCR_UNIE | TCR_TPSC_P4);
268 	_reg_write_4(SH_(TCOR1), 0xffffffff);
273 	_reg_write_2(SH_(TCR2), TCR_TPSC_P4);
274 	_reg_write_4(SH_(TCOR2), 0xffffffff);
279 	_reg_bset_1(SH_(TSTR), TSTR_STR2);