Lines Matching defs:u_int
152 u_int i_op:2; /* first-level decode */
153 u_int :30;
160 u_int :2; /* 01 */
169 u_int :2; /* 00 */
170 u_int :5;
171 u_int i_op2:3; /* second-level decode */
172 u_int :22;
177 u_int :2; /* 00 */
178 u_int i_rd:5; /* destination register */
179 u_int i_op2:3; /* opcode: UNIMP or SETHI */
180 u_int i_imm:22; /* immediate value */
185 u_int :2; /* 00 */
186 u_int i_annul:1; /* annul bit */
187 u_int i_cond:4; /* condition codes */
188 u_int i_op2:3; /* opcode: {Bi,FBf,CBc}cc */
194 u_int :2; /* 00 */
195 u_int i_annul:1; /* annul bit */
196 u_int i_cond:4; /* condition codes */
197 u_int i_op2:3; /* opcode: {BP,FBPf}cc */
198 u_int i_cc:2; /* condition code selector */
199 u_int i_pred:1; /* branch prediction bit */
205 u_int :2; /* 00 */
206 u_int i_annul:1; /* annul bit */
207 u_int :1; /* 0 */
208 u_int i_rcond:4; /* register condition */
209 u_int :3; /* 011 */
211 u_int i_pred:1; /* branch prediction bit */
212 u_int i_rs1:1; /* source register 1 */
213 u_int i_displo:16; /* branch displacement, lo bits */
230 u_int :2; /* 10 or 11 */
231 u_int i_rd:5; /* destination register */
232 u_int i_op3:6; /* second-level decode */
233 u_int i_rs1:5; /* source register 1 */
234 u_int i_low14:14; /* varies */
243 u_int :2; /* 11 only */
244 u_int i_rd:5; /* destination register */
245 u_int i_op3:6; /* second-level decode (see IOP3_mem) */
246 u_int i_rs1:5; /* source register 1 */
247 u_int i_i:1; /* immediate vs asi */
248 u_int i_low13:13; /* depend on i bit */
257 u_int :2; /* 10 or 11 */
258 u_int i_rd:5; /* destination register */
259 u_int i_op3:6; /* second-level decode */
260 u_int i_rs1:5; /* source register 1 */
261 u_int i_i:1; /* immediate bit (1) */
265 u_int :2; /* 10 or 11 */
266 u_int i_rd:5; /* destination register */
267 u_int i_op3:6; /* second-level decode */
268 u_int i_rs1:5; /* source register 1 */
269 u_int i_i:1; /* immediate vs asi */
270 u_int i_asi:8; /* asi */
271 u_int i_rs2:5; /* source register 2 */
274 u_int :2; /* 10 only (register, no memory) */
275 u_int i_rd:5; /* destination register */
276 u_int i_op3:6; /* second-level decode (see IOP3_reg) */
277 u_int i_rs1:5; /* source register 1 */
278 u_int i_opf:9; /* coprocessor 3rd-level decode */
279 u_int i_rs2:5; /* source register 2 */
293 u_int :2; /* 10 */
294 u_int i_rd:5; /* destination register */
295 u_int i_op3:6; /* second-level decode */
296 u_int i_rs1:5; /* source register 1 */
297 u_int i_low14:14; /* varies */
304 u_int :2; /* 10 */
305 u_int i_rd:5; /* destination register */
306 u_int i_op3:6; /* second-level decode */
307 u_int :1;
308 u_int i_cond:4; /* condition */
309 u_int i_opf_cc:3; /* condition code register */
310 u_int i_opf_low:6; /* third level decode */
311 u_int i_rs2:5; /* source register */
318 u_int :2; /* 10 */
319 u_int i_rd:5; /* destination register */
320 u_int i_op3:6; /* second-level decode */
321 u_int i_rs1:5; /* source register 1 */
322 u_int :1;
323 u_int i_rcond:3; /* register condition */
324 u_int i_opf_low:6;
325 u_int i_rs2:5; /* source register 2 */
Indexes created Sun Apr 12 00:22:20 UTC 2026