Lines Matching refs:UL
217 #define SCZ_PCICTRL_BUS_UNUS (1ULL << 63UL) /* bus unusable */
218 #define TOM_PCICTRL_DTO_ERR (1ULL << 62UL) /* pci discard timeout */
219 #define TOM_PCICTRL_DTO_INT (1ULL << 61UL) /* discard intr en */
220 #define SCZ_PCICTRL_ESLCK (1ULL << 51UL) /* error slot locked */
221 #define SCZ_PCICTRL_ERRSLOT (7ULL << 48UL) /* error slot */
222 #define SCZ_PCICTRL_TTO_ERR (1ULL << 38UL) /* pci trdy# timeout */
223 #define SCZ_PCICTRL_RTRY_ERR (1ULL << 37UL) /* pci rtry# timeout */
224 #define SCZ_PCICTRL_MMU_ERR (1ULL << 36UL) /* pci mmu error */
225 #define SCZ_PCICTRL_SBH_ERR (1ULL << 35UL) /* pci strm hole */
226 #define SCZ_PCICTRL_SERR (1ULL << 34UL) /* pci serr# sampled */
227 #define SCZ_PCICTRL_PCISPD (1ULL << 33UL) /* speed (0=clk/2,1=clk) */
228 #define TOM_PCICTRL_PRM (1ULL << 30UL) /* prefetch read multiple */
229 #define TOM_PCICTRL_PRO (1ULL << 29UL) /* prefetch read one */
230 #define TOM_PCICTRL_PRL (1ULL << 28UL) /* prefetch read line */
231 #define SCZ_PCICTRL_PTO (3UL << 24UL) /* pci timeout interval */
232 #define SCZ_PCICTRL_MMU_INT (1UL << 19UL) /* mmu intr en */
233 #define SCZ_PCICTRL_SBH_INT (1UL << 18UL) /* strm byte hole intr en */
234 #define SCZ_PCICTRL_EEN (1UL << 17UL) /* error intr en */
235 #define SCZ_PCICTRL_PARK (1UL << 16UL) /* bus parked */
236 #define SCZ_PCICTRL_PCIRST (1UL << 8UL) /* pci reset */
237 #define TOM_PCICTRL_ARB (0xffUL << 0UL) /* dma arb enables, tomatillo */
238 #define SCZ_PCICTRL_ARB (0x3fUL << 0UL) /* dma arb enables */
261 #define SCZ_PCIDIAG_D_BADECC (1UL << 10UL) /* disable bad ecc */
262 #define SCZ_PCIDIAG_D_BYPASS (1UL << 9UL) /* disable mmu bypass */
263 #define SCZ_PCIDIAG_D_TTO (1UL << 8UL) /* disable trdy# timeout */
264 #define SCZ_PCIDIAG_D_RTRYARB (1UL << 7UL) /* disable retry arb */
265 #define SCZ_PCIDIAG_D_RETRY (1UL << 6UL) /* disable retry lim */
266 #define SCZ_PCIDIAG_D_INTSYNC (1UL << 5UL) /* disable write sync */
267 #define SCZ_PCIDIAG_I_DMADPAR (1UL << 3UL) /* invert dma parity */
268 #define SCZ_PCIDIAG_I_PIODPAR (1UL << 2UL) /* invert pio data parity */
269 #define SCZ_PCIDIAG_I_PIOAPAR (1UL << 1UL) /* invert pio addr parity */
272 #define TOM_IOCACHE_CSR_WRT_PEN (1UL << 19UL) /* for partial line writes */
273 #define TOM_IOCACHE_CSR_NCP_RDM (1UL << 18UL) /* memory read multiple (NC) */
274 #define TOM_IOCACHE_CSR_NCP_ONE (1UL << 17UL) /* memory read (NC) */
275 #define TOM_IOCACHE_CSR_NCP_LINE (1UL << 16UL) /* memory read line (NC) */
276 #define TOM_IOCACHE_CSR_POFFSET_SHIFT (1UL << 3UL) /* prefetch offset */
277 #define TOM_IOCACHE_CSR_PEN_RDM (1UL << 2UL) /* memory read multiple */
278 #define TOM_IOCACHE_CSR_PEN_ONE (1UL << 1UL) /* memory read */
279 #define TOM_IOCACHE_CSR_PEN_LINE (1UL << 0UL) /* memory read line */
296 #define TOM_IOMMU_ERR (1UL << 24)
297 #define TOM_IOMMU_ERR_MASK (3UL << 25)
298 #define TOM_IOMMU_PROT_ERR (0UL << 25)
299 #define TOM_IOMMU_INV_ERR (1UL << 25)
300 #define TOM_IOMMU_TO_ERR (2UL << 25)
301 #define TOM_IOMMU_ECC_ERR (3UL << 25)
302 #define TOM_IOMMU_ILLTSBTBW_ERR (1UL << 27)
303 #define TOM_IOMMU_BADVA_ERR (1UL << 28)
314 #define SCZ_JBUS_ESTAR_FULL (1UL << 0) /* full speed */
315 #define SCZ_JBUS_ESTAR_HALF (1UL << 1) /* half speed */
316 #define SCZ_JBUS_ESTAR_SLOW (1UL << 5) /* 1/32 speed */
Indexes created Tue Oct 21 06:10:07 GMT 2025