Lines Matching refs:uint64_t
38 int64_t hv_api_get_version(uint64_t api_group,
39 uint64_t *major_number,
40 uint64_t *minor_number);
41 int64_t hv_api_set_version(uint64_t api_group,
42 uint64_t major_number,
43 uint64_t req_minor_number,
44 uint64_t* actual_minor_number);
61 int64_t hv_cpu_qconf(uint64_t queue, uint64_t base, uint64_t nentries);
68 int64_t hv_cpu_mondo_send(uint64_t ncpus, paddr_t cpulist, paddr_t data);
69 int64_t hv_cpu_myid(uint64_t *cpuid);
77 int64_t hv_mmu_demap_page(vaddr_t vaddr, uint64_t context, uint64_t flags);
78 int64_t hv_mmu_demap_ctx(uint64_t context, uint64_t flags);
79 int64_t hv_mmu_demap_all(uint64_t flags);
80 int64_t hv_mmu_map_perm_addr(vaddr_t vaddr, uint64_t tte, uint64_t flags);
81 int64_t hv_mmu_unmap_perm_addr(vaddr_t vaddr, uint64_t flags);
82 int64_t hv_mmu_map_addr(vaddr_t vaddr, uint64_t context, uint64_t tte,
83 uint64_t flags);
84 int64_t hv_mmu_unmap_addr(vaddr_t vaddr, uint64_t context, uint64_t flags);
98 uint64_t td_reserved;
102 uint64_t ift; /* instruction fault type */
103 uint64_t ifa; /* instruction fault address */
104 uint64_t ifc; /* instruction fault context */
105 uint64_t reserved1[5]; /* reserved */
106 uint64_t dft; /* data fault type */
107 uint64_t dfa; /* data fault address */
108 uint64_t dfc; /* data fault context */
109 uint64_t reserved2[5]; /* reserved */
112 int64_t hv_mmu_tsb_ctx0(uint64_t ntsb, paddr_t tsbptr);
113 int64_t hv_mmu_tsb_ctxnon0(uint64_t ntsb, paddr_t tsbptr);
130 int64_t hv_intr_devino_to_sysino(uint64_t devhandle, uint64_t devino,
131 uint64_t *sysino);
132 int64_t hv_intr_getenabled(uint64_t sysino, uint64_t *intr_enabled);
133 int64_t hv_intr_setenabled(uint64_t sysino, uint64_t intr_enabled);
134 int64_t hv_intr_getstate(uint64_t sysino, uint64_t *intr_state);
135 int64_t hv_intr_setstate(uint64_t sysino, uint64_t intr_state);
136 int64_t hv_intr_gettarget(uint64_t sysino, uint64_t *cpuid);
137 int64_t hv_intr_settarget(uint64_t sysino, uint64_t cpuid);
148 int64_t hv_vintr_getcookie(uint64_t devhandle, uint64_t devino,
149 uint64_t *cookie_value);
150 int64_t hv_vintr_setcookie(uint64_t devhandle, uint64_t devino,
151 uint64_t cookie_value);
152 int64_t hv_vintr_getenabled(uint64_t devhandle, uint64_t devino,
153 uint64_t *intr_enabled);
154 int64_t hv_vintr_setenabled(uint64_t devhandle, uint64_t devino,
155 uint64_t intr_enabled);
156 int64_t hv_vintr_getstate(uint64_t devhandle, uint64_t devino,
157 uint64_t *intr_state);
158 int64_t hv_vintr_setstate(uint64_t devhandle, uint64_t devino,
159 uint64_t intr_state);
160 int64_t hv_vintr_gettarget(uint64_t devhandle, uint64_t devino,
161 uint64_t *cpuid);
162 int64_t hv_vintr_settarget(uint64_t devhandle, uint64_t devino,
163 uint64_t cpuid);
171 int64_t hv_tod_get(uint64_t *tod);
172 int64_t hv_tod_set(uint64_t tod);
193 int64_t hv_soft_state_set(uint64_t software_state,
205 int64_t hv_pci_iommu_map(uint64_t devhandle, uint64_t tsbid,
206 uint64_t nttes, uint64_t io_attributes, paddr_t io_page_list_p,
207 uint64_t *nttes_mapped);
208 int64_t hv_pci_iommu_demap(uint64_t devhandle, uint64_t tsbid,
209 uint64_t nttes, uint64_t *nttes_demapped);
210 int64_t hv_pci_iommu_getmap(uint64_t devhandle, uint64_t tsbid,
211 uint64_t *io_attributes, paddr_t *r_addr);
212 int64_t hv_pci_iommu_getbypass(uint64_t devhandle, paddr_t r_addr,
213 uint64_t io_attributes, uint64_t *io_addr);
215 int64_t hv_pci_config_get(uint64_t devhandle, uint64_t pci_device,
216 uint64_t pci_config_offset, uint64_t size,
217 uint64_t *error_flag, uint64_t *data);
218 int64_t hv_pci_config_put(uint64_t devhandle, uint64_t pci_device,
219 uint64_t pci_config_offset, uint64_t size, uint64_t data,
220 uint64_t *error_flag);
231 int64_t hv_pci_msiq_conf(uint64_t devhandle, uint64_t msiqid,
232 uint64_t r_addr, uint64_t nentries);
233 int64_t hv_pci_msiq_info(uint64_t devhandle, uint64_t msiqid,
234 uint64_t *r_addr, uint64_t *nentries);
236 int64_t hv_pci_msiq_getvalid(uint64_t devhandle, uint64_t msiqid,
237 uint64_t *msiqvalid);
238 int64_t hv_pci_msiq_setvalid(uint64_t devhandle, uint64_t msiqid,
239 uint64_t msiqvalid);
246 int64_t hv_pci_msiq_getstate(uint64_t devhandle, uint64_t msiqid,
247 uint64_t *msiqstate);
248 int64_t hv_pci_msiq_setstate(uint64_t devhandle, uint64_t msiqid,
249 uint64_t msiqstate);
256 int64_t hv_pci_msiq_gethead(uint64_t devhandle, uint64_t msiqid,
257 uint64_t *msiqhead);
258 int64_t hv_pci_msiq_sethead(uint64_t devhandle, uint64_t msiqid,
259 uint64_t msiqhead);
260 int64_t hv_pci_msiq_gettail(uint64_t devhandle, uint64_t msiqid,
261 uint64_t *msiqtail);
263 int64_t hv_pci_msi_getvalid(uint64_t devhandle, uint64_t msinum,
264 uint64_t *msivalidstate);
265 int64_t hv_pci_msi_setvalid(uint64_t devhandle, uint64_t msinum,
266 uint64_t msivalidstate);
273 int64_t hv_pci_msi_getmsiq(uint64_t devhandle, uint64_t msinum,
274 uint64_t *msiqid);
275 int64_t hv_pci_msi_setmsiq(uint64_t devhandle, uint64_t msinum,
276 uint64_t msitype, uint64_t msiqid);
278 int64_t hv_pci_msi_getstate(uint64_t devhandle, uint64_t msinum,
279 uint64_t *msistate);
280 int64_t hv_pci_msi_setstate(uint64_t devhandle, uint64_t msinum,
281 uint64_t msistate);
288 int64_t hv_pci_msg_getmsiq(uint64_t devhandle, uint64_t msg,
289 uint64_t *msiqid);
290 int64_t hv_pci_msg_setmsiq(uint64_t devhandle, uint64_t msg,
291 uint64_t msiqid);
293 int64_t hv_pci_msg_getvalid(uint64_t devhandle, uint64_t msg,
294 uint64_t *msgvalidstate);
295 int64_t hv_pci_msg_setvalid(uint64_t devhandle, uint64_t msg,
296 uint64_t msgvalidstate);
313 int64_t hv_ldc_tx_qconf(uint64_t ldc_id, paddr_t base_raddr,
314 uint64_t nentries);
315 int64_t hv_ldc_tx_qinfo(uint64_t ldc_id, paddr_t *base_raddr,
316 uint64_t *nentries);
317 int64_t hv_ldc_tx_get_state(uint64_t ldc_id, uint64_t *head_offset,
318 uint64_t *tail_offset, uint64_t *channel_state);
319 int64_t hv_ldc_tx_set_qtail(uint64_t ldc_id, uint64_t tail_offset);
320 int64_t hv_ldc_rx_qconf(uint64_t ldc_id, paddr_t base_raddr,
321 uint64_t nentries);
322 int64_t hv_ldc_rx_qinfo(uint64_t ldc_id, paddr_t *base_raddr,
323 uint64_t *nentries);
324 int64_t hv_ldc_rx_get_state(uint64_t ldc_id, uint64_t *head_offset,
325 uint64_t *tail_offset, uint64_t *channel_state);
326 int64_t hv_ldc_rx_set_qhead(uint64_t ldc_id, uint64_t head_offset);
334 int64_t hv_ldc_set_map_table(uint64_t ldc_id, paddr_t base_raddr,
335 uint64_t nentries);
336 int64_t hv_ldc_get_map_table(uint64_t ldc_id, paddr_t *base_raddr,
337 uint64_t *nentries);
338 int64_t hv_ldc_copy(uint64_t ldc_id, uint64_t flags, uint64_t cookie,
346 int64_t hv_ldc_mapin(uint64_t ldc_id, uint64_t cookie, paddr_t *raddr,
347 uint64_t *perms);
348 int64_t hv_ldc_unmap(paddr_t raddr, uint64_t *perms);
357 int64_t hv_rng_ctl_read(paddr_t raddr, uint64_t *state, uint64_t *delta);
358 int64_t hv_rng_ctl_write(paddr_t raddr, uint64_t state, uint64_t timeout,
359 uint64_t *delta);
368 int64_t hv_rng_data_read_diag(paddr_t raddr, uint64_t size, uint64_t *delta);
369 int64_t hv_rng_data_read(paddr_t raddr, uint64_t *delta);
395 extern uint64_t sun4v_group_interrupt_major;
396 extern uint64_t sun4v_group_sdio_major;
398 int64_t sun4v_intr_devino_to_sysino(uint64_t, uint64_t, uint64_t *);
399 int64_t sun4v_intr_setcookie(uint64_t, uint64_t, uint64_t);
400 int64_t sun4v_intr_setenabled(uint64_t, uint64_t, uint64_t);
401 int64_t sun4v_intr_setstate(uint64_t, uint64_t, uint64_t);
402 int64_t sun4v_intr_settarget(uint64_t, uint64_t, uint64_t);
Indexes created Sun Oct 19 02:09:48 GMT 2025