Lines Matching refs:CPU_ISSUN4V
270 (CPU_ISSUN4V ? SUN4V_TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie,wc) : \
273 #define TLB_EXEC (CPU_ISSUN4V ? SUN4V_TLB_EXEC : SUN4U_TLB_EXEC)
274 #define TLB_V (CPU_ISSUN4V ? SUN4V_TLB_V : SUN4U_TLB_V)
275 #define TLB_PA_MASK (CPU_ISSUN4V ? SUN4V_TLB_PA_MASK : SUN4U_TLB_PA_MASK)
276 #define TLB_CP (CPU_ISSUN4V ? SUN4V_TLB_CP : SUN4U_TLB_CP)
277 #define TLB_P (CPU_ISSUN4V ? SUN4V_TLB_P : SUN4U_TLB_P)
278 #define TLB_W (CPU_ISSUN4V ? SUN4V_TLB_W : SUN4U_TLB_W)
279 #define TLB_ACCESS (CPU_ISSUN4V ? SUN4V_TLB_ACCESS : SUN4U_TLB_ACCESS)
280 #define TLB_MODIFY (CPU_ISSUN4V ? SUN4V_TLB_MODIFY : SUN4U_TLB_MODIFY)
281 #define TLB_REAL_W (CPU_ISSUN4V ? SUN4V_TLB_REAL_W : SUN4U_TLB_REAL_W)
282 #define TLB_TSB_LOCK (CPU_ISSUN4V ? SUN4V_TLB_TSB_LOCK : SUN4U_TLB_TSB_LOCK)
283 #define TLB_EXEC_ONLY (CPU_ISSUN4V ? SUN4V_TLB_EXEC_ONLY : SUN4U_TLB_EXEC_ONLY)
284 #define TLB_L (CPU_ISSUN4V ? 0 : SUN4U_TLB_L)
285 #define TLB_CV (CPU_ISSUN4V ? SUN4V_TLB_CV : SUN4U_TLB_CV)
286 #define TLB_IE (CPU_ISSUN4V ? SUN4V_TLB_IE : SUN4U_TLB_IE)
Indexes created Wed Oct 22 00:09:40 GMT 2025