Cross Reference: /src/sys/arch/sun3/dev/dma.c

Lines Matching refs:SC
87 	struct dma_softc *sc = device_private(self);
91 	sc->sc_dev = self;
95 	sc->intr = espdmaintr;
96 	sc->setup = dma_setup;
97 	sc->reset = dma_reset;
103 	sc->sc_bst = ca->ca_bustag;
104 	sc->sc_dmatag = ca->ca_dmatag;
105 	if (bus_space_map(sc->sc_bst, ca->ca_paddr, DMAREG_SIZE,
106 	    0, &sc->sc_bsh) != 0) {
113 	if (bus_dmamap_create(sc->sc_dmatag, MAXPHYS, 1, MAXPHYS,
114 	    0, BUS_DMA_NOWAIT, &sc->sc_dmamap) != 0) {
119 	sc->sc_rev = DMA_GCSR(sc) & D_DEV_ID;
120 	id = (sc->sc_rev >> 28) & 0xf;
128 	switch (sc->sc_rev) {
151 #define DMAWAIT(SC, COND, MSG, DONTPANIC) do if (COND) {		\
157 			__FILE__, __LINE__, DMA_GCSR(SC));		\
165 #define DMA_DRAIN(sc, dontpanic) do {					\
173 	DMAWAIT(sc, DMA_GCSR(sc) & D_R_PEND, "R_PEND", dontpanic);	\
178 	_csr = DMA_GCSR(sc);						\
180 	DMA_SCSR(sc, _csr);						\
184 	DMAWAIT(sc, DMA_GCSR(sc) & D_PACKCNT, "DRAINING", dontpanic);	\
187 #define DMA_FLUSH(sc, dontpanic) do {					\
195 	DMAWAIT(sc, DMA_GCSR(sc) & D_R_PEND, "R_PEND", dontpanic);	\
196 	_csr = DMA_GCSR(sc);						\
198 	DMA_SCSR(sc, _csr);						\
200 	DMA_SCSR(sc, _csr);						\
204 dma_reset(struct dma_softc *sc)
208 	if (sc->sc_dmamap->dm_nsegs > 0)
209 		bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap);
211 	DMA_FLUSH(sc, 1);
212 	csr = DMA_GCSR(sc);
215 	DMA_SCSR(sc, csr);
218 	/*DMAWAIT1(sc); why was this here? */
219 	csr = DMA_GCSR(sc);
221 	DMA_SCSR(sc, csr);
230 	csr = DMA_GCSR(sc);
233 	DMA_SCSR(sc, csr);
235 	sc->sc_active = 0;
245 dma_setup(struct dma_softc *sc, uint8_t **addr, size_t *len, int datain,
250 	DMA_FLUSH(sc, 0);
253 	DMA_SCSR(sc, DMA_GCSR(sc) & ~D_INT_EN);
255 	sc->sc_dmaaddr = addr;
256 	sc->sc_dmalen = len;
258 	NCR_DMA(("%s: start %d@%p,%d\n", device_xname(sc->sc_dev),
259 	    *sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0));
266 	*dmasize = sc->sc_dmasize =
267 	    uimin(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr));
269 	NCR_DMA(("%s: dmasize = %d\n", __func__, sc->sc_dmasize));
272 	if (sc->sc_dmasize) {
273 		if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap,
274 		    *sc->sc_dmaaddr, sc->sc_dmasize,
277 			    device_xname(sc->sc_dev));
278 		bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize,
280 		bus_space_write_4(sc->sc_bst, sc->sc_bsh, DMA_REG_ADDR,
281 		    sc->sc_dmamap->dm_segs[0].ds_addr);
287 	csr = DMA_GCSR(sc);
293 	DMA_SCSR(sc, csr);
306 espdmaintr(struct dma_softc *sc)
308 	struct ncr53c9x_softc *nsc = sc->sc_client;
313 	csr = DMA_GCSR(sc);
320 	    device_xname(sc->sc_dev), DMADDR(sc), bits));
324 		printf("%s: error: csr=%s\n", device_xname(sc->sc_dev), bits);
326 		DMA_SCSR(sc, csr);
328 		DMA_SCSR(sc, csr);
333 	if (sc->sc_active == 0)
336 	DMA_DRAIN(sc, 0);
340 	DMA_SCSR(sc, csr);
341 	sc->sc_active = 0;
343 	if (sc->sc_dmasize == 0) {
376 		if (resid == 0 && sc->sc_dmasize == 65536 &&
382 	trans = sc->sc_dmasize - resid;
391 		    device_xname(sc->sc_dev), trans, sc->sc_dmasize);
393 		trans = sc->sc_dmasize;
406 		cache_flush(*sc->sc_dmaaddr, trans);
409 	if (sc->sc_dmamap->dm_nsegs > 0) {
410 		bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize,
413 		bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap);
416 	*sc->sc_dmalen -= trans;
417 	*sc->sc_dmaaddr += trans;
420 	if (*sc->sc_dmalen == 0 ||
425 	dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMA_GCSR(sc) & D_WRITE);
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