Lines Matching refs:sc
53 #define DMA_GCSR(sc) \
54 bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, DMA_REG_CSR)
55 #define DMA_SCSR(sc, csr) \
56 bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, DMA_REG_CSR, (csr))
62 #define DMA_RESET(sc) (((sc)->reset)(sc))
63 #define DMA_INTR(sc) (((sc)->intr)(sc))
64 #define DMA_SETUP(sc, a, l, d, s) (((sc)->setup)(sc, a, l, d, s))
67 #define DMA_ISACTIVE(sc) ((sc)->sc_active)
69 #define DMA_ENINTR(sc) do { \
70 uint32_t _csr = DMA_GCSR(sc); \
72 DMA_SCSR(sc, _csr); \
75 #define DMA_ISINTR(sc) (DMA_GCSR(sc) & (D_INT_PEND|D_ERR_PEND))
77 #define DMA_GO(sc) do { \
78 uint32_t _csr = DMA_GCSR(sc); \
80 DMA_SCSR(sc, _csr); \
81 sc->sc_active = 1; \
84 #define DMA_STOP(sc) do { \
85 uint32_t _csr = DMA_GCSR(sc); \
87 DMA_SCSR(sc, _csr); \
88 sc->sc_active = 0; \
Indexes created Sat Oct 25 16:10:12 GMT 2025