Cross Reference: /src/sys/arch/sun3/sun3x/pmap.c

Lines Matching defs:a_tbl
1098 	a_tmgr_t *a_tbl;
1102 		a_tbl = &Atmgrbase[i];
1108 		a_tbl->at_parent = NULL;
1109 		a_tbl->at_wcnt = a_tbl->at_ecnt = 0;
1112 		a_tbl->at_dtbl = &mmuAbase[i * MMU_A_TBL_SIZE];
1119 		memcpy(a_tbl->at_dtbl, kernAbase,
1126 		TAILQ_INSERT_TAIL(&a_pool, a_tbl, at_link);
1358 free_a_table(a_tmgr_t *a_tbl, bool relink)
1370 	 * flush_atc_crp(mmu_vtop(a_tbl->dte));
1376 	 * a_tbl->parent->atc_flushq[0] = 0;
1387 	at_wired = a_tbl->at_wcnt;
1388 	if (a_tbl->at_ecnt) {
1389 		dte = a_tbl->at_dtbl;
1419 					a_tbl->at_wcnt--;
1423 		a_tbl->at_ecnt = 0;
1425 	KASSERT(a_tbl->at_wcnt == 0);
1428 		a_tbl->at_parent = NULL;
1430 			TAILQ_REMOVE(&a_pool, a_tbl, at_link);
1431 		TAILQ_INSERT_HEAD(&a_pool, a_tbl, at_link);
1605 pmap_stroll(pmap_t pmap, vaddr_t va, a_tmgr_t **a_tbl, b_tmgr_t **b_tbl,
1616 	*a_tbl = pmap->pm_a_tmgr;
1617 	if (*a_tbl == NULL)
1623 	a_dte = &((*a_tbl)->at_dtbl[*a_idx]);
1661 	a_tmgr_t *a_tbl;         /* A: long descriptor table manager  */
1732 	a_tbl = pmap->pm_a_tmgr;
1733 	if (a_tbl == NULL) {
1738 		a_tbl = get_a_table();
1739 		a_tbl->at_parent = pmap;
1746 		pmap->pm_a_tmgr = a_tbl;
1747 		pmap->pm_a_phys = mmu_vtop(a_tbl->at_dtbl);
1767 		if (wired && !a_tbl->at_wcnt)
1768 			TAILQ_REMOVE(&a_pool, a_tbl, at_link);
1777 	a_dte = &a_tbl->at_dtbl[a_idx]; /* Retrieve descriptor from table */
1783 		 * a_tbl -> +-+-+-+-+-+-+-+-+-+-+-+- *
1802 			a_tbl->at_wcnt++;
1811 		a_tbl->at_ecnt++; /* Update parent's valid entry count */
1814 		b_tbl->bt_parent = a_tbl;
1823 			a_tbl->at_wcnt++;
1923 						if (--a_tbl->at_wcnt == 0) {
2039 			TAILQ_INSERT_TAIL(&a_pool, a_tbl, at_link);
2265 	a_tmgr_t *a_tbl;
2309 	if ((a_tbl = pmap->pm_a_tmgr) == NULL)
2320 		if (b_tbl || MMU_VALID_DT(a_tbl->at_dtbl[a_idx])) {
2322 		    b_tbl = (b_tmgr_t *) a_tbl->at_dtbl[a_idx].addr.raw;
2384 	a_tmgr_t *a_tbl;
2398 	if (pmap_stroll(pmap, va, &a_tbl, &b_tbl, &c_tbl, &pte, &a_idx,
2424 			if (--a_tbl->at_wcnt == 0) {
2425 				TAILQ_INSERT_TAIL(&a_pool, a_tbl, at_link);
2940 	a_tmgr_t	*a_tbl;
2948 	if (pmap_stroll(pmap, va, &a_tbl, &b_tbl, &c_tbl,
3049 pmap_remove_a(a_tmgr_t *a_tbl, vaddr_t sva, vaddr_t eva)
3091 	at_wired = a_tbl->at_wcnt;
3102 		a_dte = &a_tbl->at_dtbl[idx];
3132 				a_tbl->at_wcnt--;
3141 				a_tbl->at_ecnt--;
3158 		a_dte = &a_tbl->at_dtbl[idx];
3182 					a_tbl->at_wcnt--;
3190 				a_tbl->at_ecnt--;
3203 		a_dte = &a_tbl->at_dtbl[idx];
3227 				a_tbl->at_wcnt--;
3235 				a_tbl->at_ecnt--;
3244 	if (a_tbl->at_ecnt == 0) {
3245 		KASSERT(a_tbl->at_wcnt == 0);
3246 		a_tbl->at_parent = NULL;
3248 			TAILQ_REMOVE(&a_pool, a_tbl, at_link);
3249 		TAILQ_INSERT_HEAD(&a_pool, a_tbl, at_link);
3257 		if (at_wired && a_tbl->at_wcnt == 0)
3258 			TAILQ_INSERT_TAIL(&a_pool, a_tbl, at_link);
3644 	a_tmgr_t *a_tbl;
3655 	a_tbl = pmap->pm_a_tmgr;
3659 	    if (MMU_VALID_DT(a_tbl->at_dtbl[a_idx])) {
3660 	        b_tbl = mmuB2tmgr(mmu_ptov(a_tbl->at_dtbl[a_idx].addr.raw));
3794 flush_atc_crp(int a_tbl)
3802 	rp.addr.raw = (unsigned int) a_tbl;