Lines Matching refs:SCN_REG
43 /* per-channel regs (channel B's at SCN_REG(8-11)) */
44 #define CH_MR(x) SCN_REG(0 + 8*(x)) /* rw mode register */
45 #define CH_SR(x) SCN_REG(1 + 8*(x)) /* ro status register */
46 #define CH_CSR(x) SCN_REG(1 + 8*(x)) /* wo clock select reg */
47 #define CH_CR(x) SCN_REG(2 + 8*(x)) /* wo command reg */
48 #define CH_DAT(x) SCN_REG(3 + 8*(x)) /* rw data reg */
51 #define DU_IPCR SCN_REG(4) /* ro input port change reg */
52 #define DU_ACR SCN_REG(4) /* wo aux control reg */
53 #define DU_ISR SCN_REG(5) /* ro interrupt stat reg */
54 #define DU_IMR SCN_REG(5) /* wo interrupt mask reg */
55 #define DU_CTUR SCN_REG(6) /* rw counter timer upper reg */
56 #define DU_CTLR SCN_REG(7) /* rw counter timer lower reg */
57 /* SCN_REG(8-11) channel b (see above) */
58 /* SCN_REG(12): reserved */
59 #define DU_IP SCN_REG(13) /* ro input port */
60 #define DU_OPCR SCN_REG(13) /* wo output port cfg reg */
61 #define DU_CSTRT SCN_REG(14) /* ro start C/T cmd */
62 #define DU_OPSET SCN_REG(14) /* wo output port set */
63 #define DU_CSTOP SCN_REG(15) /* ro stop C/T cmd */
64 #define DU_OPCLR SCN_REG(15) /* wo output port reset */
Indexes created Mon Oct 13 21:09:55 GMT 2025