Cross Reference: /src/sys/arch/x68k/dev/intio

Lines Matching defs:dmac
33  * Hitachi HD63450 (= Motorola MC68450) DMAC driver for x68k.
80 CFATTACH_DECL_NEW(dmac, sizeof(struct dmac_softc),
90 	if (strcmp(ia->ia_name, "dmac") != 0)
122 		panic("IO map for DMAC corruption??");
131 	aprint_normal(": HD63450 DMAC\n");
168 	struct dmac_softc *dmac = device_private(intio->sc_dmac);
169 	struct dmac_channel_stat *chan = &dmac->sc_channels[ch];
174 	aprint_normal_dev(dmac->sc_dev, "allocating ch %d for %s.\n",
179 		panic("Invalid DMAC channel.");
181 		panic("DMAC: channel in use.");
183 		panic("DMAC: wrong user name.");
187 	/* allocate the DMAC arraychaining map */
193 		panic("DMAC: cannot alloc DMA safe memory");
200 		panic("DMAC: cannot map DMA safe memory");
216 	bus_space_write_1(dmac->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff);
217 	bus_space_write_1(dmac->sc_bst, chan->ch_bht,
219 	bus_space_write_1(dmac->sc_bst, chan->ch_bht, DMAC_REG_CPR, 0);
227 	bus_space_write_1(dmac->sc_bst, chan->ch_bht,
229 	bus_space_write_1(dmac->sc_bst, chan->ch_bht,
231 	bus_space_write_1(dmac->sc_bst, chan->ch_bht,
235 	bus_space_write_1(dmac->sc_bst, chan->ch_bht, DMAC_REG_NIVR, normalv);
236 	bus_space_write_1(dmac->sc_bst, chan->ch_bht, DMAC_REG_EIVR, errorv);
248 	struct dmac_softc *dmac = device_private(intio->sc_dmac);
249 	struct dmac_channel_stat *chan = &dmac->sc_channels[ch];
291 dmac_load_xfer(struct dmac_softc *dmac, struct dmac_dma_xfer *xf)
304 	bus_space_write_1(dmac->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff);
305 	bus_space_write_1(dmac->sc_bst, chan->ch_bht, DMAC_REG_SCR, xf->dx_scr);
306 	bus_space_write_1(dmac->sc_bst, chan->ch_bht,
308 	bus_space_write_4(dmac->sc_bst, chan->ch_bht,
319 	struct dmac_softc *dmac = chan->ch_softc;
327 	dmac_load_xfer(dmac, xf);
340 dmac_start_xfer(struct dmac_softc *dmac, struct dmac_dma_xfer *xf)
342 	return dmac_start_xfer_offset(dmac, xf, 0, 0);
346 dmac_start_xfer_offset(struct dmac_softc *dmac, struct dmac_dma_xfer *xf,
386 	/* program DMAC in single block mode or array chainning mode */
394 		csr = bus_space_read_1(dmac->sc_bst, chan->ch_bht, DMAC_REG_CSR);
397 			bus_space_write_4(dmac->sc_bst, chan->ch_bht,
399 			bus_space_write_2(dmac->sc_bst, chan->ch_bht,
404 			bus_space_write_4(dmac->sc_bst, chan->ch_bht,
406 			bus_space_write_2(dmac->sc_bst, chan->ch_bht,
414 		c = dmac_program_arraychain(dmac->sc_dev, xf, offset, size);
415 		bus_space_write_4(dmac->sc_bst, chan->ch_bht,
417 		bus_space_write_2(dmac->sc_bst, chan->ch_bht,
420 		panic("DMAC: unexpected use of arraychaining mode");
424 	bus_space_write_1(dmac->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff);
437 	bus_space_write_1(dmac->sc_bst, chan->ch_bht, DMAC_REG_CCR, go);
535 		printf("DMAC transfer error CSR=%02x, CER=%02x\n", csr, cer);
550 dmac_abort_xfer(struct dmac_softc *dmac, struct dmac_dma_xfer *xf)
554 	bus_space_write_1(dmac->sc_bst, chan->ch_bht, DMAC_REG_CCR,
556 	bus_space_write_1(dmac->sc_bst, chan->ch_bht, DMAC_REG_CSR, 0xff);
572 	printf("DMAC channel %d registers\n", chan->ch_channel);
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