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1 /* $NetBSD: imc.c,v 1.6 2023/05/10 00:07:49 riastradh Exp $ */
68 __KERNEL_RCSID(0, "$NetBSD: imc.c,v 1.6 2023/05/10 00:07:49 riastradh Exp $");
87  * "Integrated Memory Controllers" (iMCs), and each iMC contains two separate
89  * for reading the "Thermal Sensor on DIMM" (TSODs). The iMC SMBus controllers
93  * The publicly available documentation for the iMC SMBus controllers can be
107  * The iMC SMBus controllers do not support interrupts (thus, they must be
108  * polled for IO completion). All of the iMC registers are in PCI configuration
169 	    "Intel Sandybridge Xeon iMC 0 SMBus controllers"	},
171 	    "Intel Ivybridge Xeon iMC 0 SMBus controllers"	},
173 	    "Intel Haswell Xeon iMC 0 SMBus controllers"	},
175 	    "Intel Haswell Xeon iMC 1 SMBus controllers"	},
177 	    "Intel Broadwell Xeon iMC 0 SMBus controllers"	},
179 	    "Intel Broadwell Xeon iMC 1 SMBus controllers"	},
190 CFATTACH_DECL3_NEW(imc, sizeof(struct imc_softc),
319  * IMC controllers.  The softc argument is for the imcsmb child device
321  * i2cbus instances on a given IMC (or all instances on all IMCs), you
355 MODULE(MODULE_CLASS_DRIVER, imc, "pci");