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Lines Matching refs:L2

466  * For PAE, we need an L3 page, a single contiguous L2 "superpage" of 4 pages
545 	 * Now compute how many L2 pages we need exactly. This is useful only
555 	 * One more L2 page: we'll allocate several pages after kva_start
557 	 * counted here. It's not a big issue to allocate one more L2 as
565 	 * Install bootstrap pages. We may need more L2 pages than will
580 	 * Make sure the number of L2 pages we have is enough to map everything
609  * old_count is # of old tables (including L4, L3 and L2).
617 L2, *pte;
699 	/* L2 */
700 	L2 = (pd_entry_t *)avail;
701 	memset(L2, 0, PAGE_SIZE);
704 	/* link L3->L2 */
705 	addr = ((u_long)L2) - KERNBASE;
718 	 * Our PAE-style level 2, 5 contiguous pages (4 L2 + 1 shadow).
720 	 * Physical layout: | 3 * USERLAND L2 | L2 KERN SHADOW | L2 KERN |
722 	 * However, we enter L3[3] into L2 KERN, and not L2 KERN SHADOW.
723 	 * This way, L2[L2_SLOT_KERN] always points to the shadow.
725 	L2 = (pd_entry_t *)avail;
726 	memset(L2, 0, PAGE_SIZE * 5);
730 	 * Link L2 pages in L3, with a special case for L2 KERN. Xen doesn't
733 	addr = ((u_long)L2) - KERNBASE;
820 		L2[pl2_pi(cur_page)] = xpmap_ptom_masked(addr) | PTE_W | PTE_P;
836 	xen_bt_set_readonly((vaddr_t)L2);
838 	/* Copy L2 KERN into L2 KERN SHADOW, and reference the latter in cpu0. */
839 	memcpy(&L2[L2_SLOT_KERN + NPDPG], &L2[L2_SLOT_KERN], PAGE_SIZE);
840 	cpu_info_primary.ci_kpm_pdir = &L2[L2_SLOT_KERN + NPDPG];
846 	 * the first 4 L2 pages, which includes the kernel's L2 shadow. But we
850 	addr = (u_long)L2 - KERNBASE;
852 		L2[PDIR_SLOT_PTE + i] = xpmap_ptom_masked(addr) | PTE_P |
856 	/* Mark tables RO, and pin L2 KERN SHADOW. */
857 	addr = (u_long)L2 - KERNBASE;
859 		xen_bt_set_readonly(((vaddr_t)L2) + PAGE_SIZE * i);
862 		addr = (u_long)L2 - KERNBASE + 3 * PAGE_SIZE;
883 	PDPpaddr = (u_long)L2 - KERNBASE; /* PDP is the L2 with PAE */
900 		addr = (u_long)L2 - KERNBASE + PAGE_SIZE * 3;
902 		    xpmap_ptom(((vaddr_t)&L2[PDIR_SLOT_PTE + 3]) - KERNBASE),
917 	addr = xpmap_mtop((paddr_t)L2[pl2_pi(page)] & PTE_4KFRAME);