Lines Matching refs:ld4
377 * We could do these sixteen LD4-into-lane instructions instead
384 * than sixteen LD4 instructions, even if we interleave the LD1
387 ld4 {v16.s,v17.s,v18.s,v19.s}[0], [x1], #16
388 ld4 {v20.s,v21.s,v22.s,v23.s}[0], [x1], #16
389 ld4 {v24.s,v25.s,v26.s,v27.s}[0], [x1], #16
390 ld4 {v28.s,v29.s,v30.s,v31.s}[0], [x1], #16
391 ld4 {v16.s,v17.s,v18.s,v19.s}[1], [x1], #16
392 ld4 {v20.s,v21.s,v22.s,v23.s}[1], [x1], #16
393 ld4 {v24.s,v25.s,v26.s,v27.s}[1], [x1], #16
394 ld4 {v28.s,v29.s,v30.s,v31.s}[1], [x1], #16
395 ld4 {v16.s,v17.s,v18.s,v19.s}[2], [x1], #16
396 ld4 {v20.s,v21.s,v22.s,v23.s}[2], [x1], #16
397 ld4 {v24.s,v25.s,v26.s,v27.s}[2], [x1], #16
398 ld4 {v28.s,v29.s,v30.s,v31.s}[2], [x1], #16
399 ld4 {v16.s,v17.s,v18.s,v19.s}[3], [x1], #16
400 ld4 {v20.s,v21.s,v22.s,v23.s}[3], [x1], #16
401 ld4 {v24.s,v25.s,v26.s,v27.s}[3], [x1], #16
402 ld4 {v28.s,v29.s,v30.s,v31.s}[3], [x1], #16