Cross Reference: /src/sys/dev/acpi/apei.c

Lines Matching defs:PE
511 	const struct cper_pcie_error *PE = buf;
521 	    CPER_PCIE_ERROR_VALIDATION_BITS_FMT, PE->ValidationBits);
523 	if (PE->ValidationBits & CPER_PCIE_ERROR_VALID_PORT_TYPE) {
524 		const uint32_t t = PE->PortType;
536 	if (PE->ValidationBits & CPER_PCIE_ERROR_VALID_VERSION) {
539 		    ctx, PE->Version);
541 	if (PE->ValidationBits & CPER_PCIE_ERROR_VALID_COMMAND_STATUS) {
572 		    "\0", PE->CommandStatus);
576 	if (PE->ValidationBits & CPER_PCIE_ERROR_VALID_DEVICE_ID) {
590 		    le16dec(PE->DeviceID.VendorID),
591 		    le16dec(PE->DeviceID.DeviceID),
592 		    (PE->DeviceID.ClassCode[0] |	/* le24dec */
593 			((uint32_t)PE->DeviceID.ClassCode[1] << 8) |
594 			((uint32_t)PE->DeviceID.ClassCode[2] << 16)),
595 		    PE->DeviceID.Function, PE->DeviceID.Device,
596 		    le16dec(PE->DeviceID.Segment), PE->DeviceID.Bus,
597 		    PE->DeviceID.SecondaryBus, le16dec(PE->DeviceID.Slot),
598 		    PE->DeviceID.Reserved0);
600 	if (PE->ValidationBits & CPER_PCIE_ERROR_VALID_DEVICE_SERIAL) {
602 		    ctx, PE->DeviceSerial);
604 	if (PE->ValidationBits & CPER_PCIE_ERROR_VALID_BRIDGE_CONTROL_STATUS) {
607 		    "\n", ctx, PE->BridgeControlStatus);
609 	if (PE->ValidationBits & CPER_PCIE_ERROR_VALID_CAPABILITY_STRUCTURE) {
611 		char hex[9*sizeof(PE->CapabilityStructure)/4];
618 		__CTASSERT(sizeof(PE->CapabilityStructure) % 4 == 0);
619 		for (i = 0; i < sizeof(PE->CapabilityStructure)/4; i++) {
621 			    le32dec(&PE->CapabilityStructure[4*i]));
632 		dcsr = le32dec(&PE->CapabilityStructure[PCIE_DCSR]);
652 	if (PE->ValidationBits & CPER_PCIE_ERROR_VALID_AER_INFO) {
656 		char hex[9*sizeof(PE->AERInfo)/4];
664 		__CTASSERT(sizeof(PE->AERInfo) % 4 == 0);
665 		for (i = 0; i < sizeof(PE->AERInfo)/4; i++) {
667 			    le32dec(&PE->AERInfo[4*i]));
706 		uc_status = le32dec(&PE->AERInfo[PCI_AER_UC_STATUS]);
707 		uc_sev = le32dec(&PE->AERInfo[PCI_AER_UC_SEVERITY]);
708 		cor_status = le32dec(&PE->AERInfo[PCI_AER_COR_STATUS]);
709 		control = le32dec(&PE->AERInfo[PCI_AER_CAP_CONTROL]);
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