Lines Matching defs:dh
286 cs4231_ebus_dma_reset(bus_space_tag_t dt, bus_space_handle_t dh)
292 bus_space_write_4(dt, dh, EBUS_DMAC_DCSR, EBDMA_RESET | EBDMA_TC);
295 csr = bus_space_read_4(dt, dh, EBUS_DMAC_DCSR);
307 bus_space_write_4(dt, dh, EBUS_DMAC_DCSR, csr & ~EBDMA_RESET);
314 bus_space_handle_t dh)
321 bus_space_write_4(dt, dh, EBUS_DMAC_DNBR, (u_int32_t)dmasize);
322 bus_space_write_4(dt, dh, EBUS_DMAC_DNAR, (u_int32_t)dmaaddr);
327 * Trigger transfer "t" using DMA controller at "dt"/"dh".
335 bus_space_handle_t dh,
353 ret = cs4231_ebus_dma_reset(dt, dh);
357 csr = bus_space_read_4(dt, dh, EBUS_DMAC_DCSR);
358 bus_space_write_4(dt, dh, EBUS_DMAC_DCSR,
364 bus_space_write_4(dt, dh, EBUS_DMAC_DNBR, (uint32_t)dmasize);
365 bus_space_write_4(dt, dh, EBUS_DMAC_DNAR, (uint32_t)dmaaddr);
368 cs4231_ebus_dma_advance(t, dt, dh);
482 bus_space_handle_t dh, void *sih)
490 csr = bus_space_read_4(dt, dh, EBUS_DMAC_DCSR);
491 bus_space_write_4(dt, dh, EBUS_DMAC_DCSR, csr);
500 cs4231_ebus_dma_reset(dt, dh);
518 cs4231_ebus_dma_advance(t, dt, dh);