Lines Matching defs:au
60 au8522_reset(struct au8522 *au)
62 return au8522_write_1(au, 0xa4, 1 << 5);
66 au8522_read_1(struct au8522 *au, uint16_t reg, uint8_t *val)
73 error = iic_exec(au->i2c, I2C_OP_WRITE, au->i2c_addr,
77 return iic_exec(au->i2c, I2C_OP_READ, au->i2c_addr,
82 au8522_write_1(struct au8522 *au, uint16_t reg, uint8_t val)
89 return iic_exec(au->i2c, I2C_OP_WRITE, au->i2c_addr,
94 au8522_set_vinput(struct au8522 *au, au8522_vinput_t vi)
98 au8522_write_1(au, AU8522_REG_MODCLKCTL, AU8522_MODCLKCTL_CVBS);
99 au8522_write_1(au, AU8522_REG_PGACTL, 0x00);
100 au8522_write_1(au, AU8522_REG_CLAMPCTL, 0x0e);
101 au8522_write_1(au, AU8522_REG_PGACTL, 0x10);
102 au8522_write_1(au, AU8522_REG_INPUTCTL,
105 au8522_set_common(au, vi);
107 au8522_write_1(au, AU8522_REG_SYSMODCTL0,
111 au8522_write_1(au, AU8522_REG_MODCLKCTL,
113 au8522_write_1(au, AU8522_REG_INPUTCTL,
115 au8522_write_1(au, AU8522_REG_CLAMPCTL, 0x00);
117 au8522_set_common(au, vi);
119 au8522_write_1(au, AU8522_REG_SYSMODCTL0,
124 au8522_write_1(au, AU8522_REG_MODCLKCTL, AU8522_MODCLKCTL_CVBS);
125 au8522_write_1(au, AU8522_REG_PGACTL, 0x00);
126 au8522_write_1(au, AU8522_REG_CLAMPCTL, 0x0e);
127 au8522_write_1(au, AU8522_REG_PGACTL, 0x10);
128 au8522_write_1(au, AU8522_REG_INPUTCTL,
131 au8522_set_common(au, vi);
133 au8522_write_1(au, AU8522_REG_SYSMODCTL0,
145 au8522_set_common(struct au8522 *au, au8522_vinput_t vi)
147 au8522_write_1(au, AU8522_REG_INTMASK, 0x00);
148 au8522_write_1(au, AU8522_REG_VIDEOMODE, vi == AU8522_VINPUT_SVIDEO ?
150 au8522_write_1(au, AU8522_REG_TV_PGA, AU8522_TV_PGA_CVBS);
154 au8522_set_ainput(struct au8522 *au, au8522_ainput_t ai)
157 au8522_write_1(au, AU8522_REG_AUDIO_VOL_L, 0x00);
158 au8522_write_1(au, AU8522_REG_AUDIO_VOL_R, 0x00);
159 au8522_write_1(au, AU8522_REG_AUDIO_VOL, 0x00);
163 au8522_write_1(au, AU8522_REG_SYSMODCTL0,
165 au8522_write_1(au, AU8522_REG_AUDIO_MODE, 0x82);
166 au8522_write_1(au, AU8522_REG_SYSMODCTL1,
168 au8522_write_1(au, AU8522_REG_AUDIO_FREQ, 0x03);
169 au8522_write_1(au, AU8522_REG_I2S_CTL2, 0xc2);
171 au8522_write_1(au, AU8522_REG_AUDIO_VOL_L, 0x7f);
172 au8522_write_1(au, AU8522_REG_AUDIO_VOL_R, 0x7f);
173 au8522_write_1(au, AU8522_REG_AUDIO_VOL, 0xff);
176 au8522_write_1(au, AU8522_REG_USBEN, 0x00);
177 au8522_write_1(au, AU8522_REG_AUDIO_VOL_L, 0x7f);
178 au8522_write_1(au, AU8522_REG_AUDIO_VOL_R, 0x7f);
179 au8522_write_1(au, AU8522_REG_AUDIO_MODE, 0x40);
180 au8522_write_1(au, AU8522_REG_SYSMODCTL1,
182 au8522_write_1(au, AU8522_REG_AUDIO_FREQ, 0x03);
183 au8522_write_1(au, AU8522_REG_I2S_CTL2, 0x02);
184 au8522_write_1(au, AU8522_REG_SYSMODCTL0,
194 au8522_set_if(struct au8522 *au)
199 switch (au->if_freq) {
206 aprint_error_dev(au->parent, "au8522: unsupported if freq %dHz\n", au->if_freq);
211 au8522_write_1(au, 0x80b5 + n, ifinit[n]);
219 struct au8522 *au;
221 au = kmem_alloc(sizeof(*au), KM_SLEEP);
222 au->parent = parent;
223 au->i2c = i2c;
224 au->i2c_addr = addr;
225 au->current_modulation = -1;
226 au->if_freq = if_freq;
228 if (au8522_reset(au))
230 if (au8522_write_1(au, AU8522_REG_TUNERCTL, AU8522_TUNERCTL_EN))
233 return au;
236 kmem_free(au, sizeof(*au));
241 au8522_close(struct au8522 *au)
243 kmem_free(au, sizeof(*au));
247 au8522_enable(struct au8522 *au, bool enable)
250 au8522_write_1(au, AU8522_REG_SYSMODCTL0,
253 au8522_write_1(au, AU8522_REG_SYSMODCTL0,
256 au8522_write_1(au, AU8522_REG_SYSMODCTL0,
262 au8522_set_input(struct au8522 *au, au8522_vinput_t vi, au8522_ainput_t ai)
264 au8522_reset(au);
267 au8522_set_vinput(au, vi);
269 au8522_set_ainput(au, ai);
273 au8522_get_signal(struct au8522 *au)
277 if (au8522_read_1(au, AU8522_REG_STATUS, &status))
287 au8522_set_audio(struct au8522 *au, bool onoff)
290 au8522_write_1(au, AU8522_REG_AUDIO_VOL_L, 0x7f);
291 au8522_write_1(au, AU8522_REG_AUDIO_VOL_R, 0x7f);
292 au8522_write_1(au, AU8522_REG_AUDIO_VOL, 0xff);
294 au8522_write_1(au, AU8522_REG_AUDIO_VOL_L, 0x00);
295 au8522_write_1(au, AU8522_REG_AUDIO_VOL_R, 0x00);
296 au8522_write_1(au, AU8522_REG_AUDIO_VOL, 0x00);
301 au8522_set_modulation(struct au8522 *au, fe_modulation_t modulation)
325 au8522_write_1(au, modtab[n].reg, modtab[n].val);
327 au8522_set_if(au);
329 au->current_modulation = modulation;
335 au8522_set_gate(struct au8522 *au, bool onoff)
337 au8522_write_1(au, AU8522_REG_TUNERCTL, onoff ? AU8522_TUNERCTL_EN : 0);
341 au8522_get_dtv_status(struct au8522 *au)
346 switch (au->current_modulation) {
348 if (au8522_read_1(au, 0x4088, &val))
358 if (au8522_read_1(au, 0x4541, &val))
381 au8522_get_snr(struct au8522 *au)
389 switch (au->current_modulation) {
409 if (au8522_read_1(au, snrreg, &val))
Indexes created Wed Oct 01 19:09:53 GMT 2025