Lines Matching refs:zl
75 struct zl10353 *zl;
77 zl = kmem_zalloc(sizeof(*zl), KM_SLEEP);
78 zl->zl_i2c = i2c;
79 zl->zl_i2c_addr = addr;
80 zl->zl_parent = parent;
82 zl->zl_freq = ZL10353_DEFAULT_INPUT_FREQ;
83 zl->zl_clock = ZL10353_DEFAULT_CLOCK_MHZ;
85 if (zl10353_reset(zl, true) != 0) {
86 zl10353_close(zl);
90 if (zl10353_probe(zl) != 0) {
91 zl10353_close(zl);
95 return zl;
99 zl10353_close(struct zl10353 *zl)
101 kmem_free(zl, sizeof(*zl));
105 zl10353_probe(struct zl10353 *zl)
110 if ((rv = zl10353_read(zl, ZL10353_REG_ID, &val)) != 0)
116 zl->zl_name = "Intel CE6230";
120 zl->zl_name = "Intel CE6231";
124 zl->zl_name = "Zarlink ZL10353";
128 aprint_error_dev(zl->zl_parent, "unknown chip 0x%02x\n", val);
132 aprint_verbose_dev(zl->zl_parent, "found %s at i2c "
133 "addr 0x%02x\n", zl->zl_name, zl->zl_i2c_addr);
139 zl10353_read(struct zl10353 *zl, uint8_t reg, uint8_t *valp)
144 if ((rv = iic_acquire_bus(zl->zl_i2c, 0)) != 0)
147 rv = iic_exec(zl->zl_i2c, op, zl->zl_i2c_addr, ®, 1, valp, 1, 0);
148 iic_release_bus(zl->zl_i2c, 0);
154 zl10353_write(struct zl10353 *zl, uint8_t reg, uint8_t val)
160 if ((rv = iic_acquire_bus(zl->zl_i2c, 0)) != 0)
163 rv = iic_exec(zl->zl_i2c, op, zl->zl_i2c_addr, cmd, 2, NULL, 0, 0);
164 iic_release_bus(zl->zl_i2c, 0);
170 zl10353_reset(struct zl10353 *zl, bool hard)
196 if ((rv = zl10353_write(zl, reset[i].reg, reset[i].val)) != 0)
232 zl10353_set_params(struct zl10353 *zl,const struct dvb_frontend_parameters *fp)
237 if ((rv = zl10353_reset(zl, false)) != 0)
241 if ((rv = zl10353_set_agc(zl, fp)) != 0)
245 if ((rv = zl10353_set_bw(zl, fp->u.ofdm.bandwidth)) != 0)
249 if ((rv = zl10353_set_rate(zl)) != 0)
253 if ((rv = zl10353_set_freq(zl)) != 0)
257 if ((rv = zl10353_set_tps(zl, fp)) != 0)
264 zl10353_set_fsm(struct zl10353 *zl)
266 return zl10353_write(zl, ZL10353_REG_FSM, ZL10353_FSM_START);
281 zl10353_set_agc(struct zl10353 *zl, const struct dvb_frontend_parameters *fp)
287 if ((rv = zl10353_write(zl, ZL10353_REG_AGC_TARGET, val)) != 0)
299 return zl10353_write(zl, ZL10353_REG_AGC_CTRL, val);
303 zl10353_set_bw(struct zl10353 *zl, fe_bandwidth_t bw)
314 zl->zl_bw = 6;
321 zl->zl_bw = 7;
328 zl->zl_bw = 8;
332 zl->zl_bw = 0;
336 if ((rv = zl10353_write(zl, ZL10353_REG_BW_1, val[0])) != 0)
339 if ((rv = zl10353_write(zl, ZL10353_REG_BW_2, val[1])) != 0)
342 if ((rv = zl10353_write(zl, ZL10353_REG_BW_3, val[2])) != 0)
349 zl10353_set_rate(struct zl10353 *zl)
355 KASSERT(zl->zl_bw >= 6 && zl->zl_bw <= 8);
356 KASSERT(zl->zl_clock > 0 && zl->zl_freq > 0);
358 val = zl->zl_bw * c;
359 val += zl->zl_clock >> 1;
360 val /= zl->zl_clock;
363 if ((rv = zl10353_write(zl, ZL10353_REG_RATE_1, val >> 8)) != 0)
366 return zl10353_write(zl, ZL10353_REG_RATE_2, val & 0xff);
370 zl10353_set_freq(struct zl10353 *zl)
372 const uint16_t val = zl->zl_freq;
375 if ((rv = zl10353_write(zl, ZL10353_REG_FREQ_1, val >> 8)) != 0)
378 return zl10353_write(zl, ZL10353_REG_FREQ_2, val & 0xff);
382 zl10353_set_tps(struct zl10353 *zl, const struct dvb_frontend_parameters *fp)
406 if ((rv = zl10353_write(zl, ZL10353_REG_TPS_1, val >> 8)) != 0)
409 if ((rv = zl10353_write(zl, ZL10353_REG_TPS_2, val & 0xff)) != 0)
415 aprint_error_dev(zl->zl_parent, "failed to set "
416 "tps for %s (err %d)\n", zl->zl_name, rv);
591 zl10353_get_status(struct zl10353 *zl)
597 if (zl10353_read(zl, ZL10353_REG_STATUS_LOCK, &val) == 0) {
609 if (zl10353_read(zl, ZL10353_REG_STATUS_SYNC, &val) == 0) {
615 if (zl10353_read(zl, ZL10353_REG_STATUS_SIGNAL, &val) == 0) {
625 zl10353_get_signal_strength(struct zl10353 *zl)
629 if (zl10353_read(zl, ZL10353_REG_SIGSTR_1, &val1) != 0)
632 if (zl10353_read(zl, ZL10353_REG_SIGSTR_2, &val2) != 0)
639 zl10353_get_snr(struct zl10353 *zl)
643 if (zl10353_read(zl, ZL10353_REG_SNR, &val) != 0)
Indexes created Fri Oct 31 11:10:07 GMT 2025