Lines Matching defs:scsi_cfg1
654 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
658 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
681 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
685 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
1180 u_int16_t scsi_cfg1;
1184 * Determine SCSI_CFG1 Microcode Default Value.
1186 * The microcode will set the SCSI_CFG1 register using this value
1190 /* Read current SCSI_CFG1 Register value. */
1191 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1);
1196 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
1197 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) {
1214 if ((scsi_cfg1 & ADW_DIFF_MODE) &&
1215 (scsi_cfg1 & ADW_DIFF_SENSE) == 0) {
1225 * is ready to be 'ored' into SCSI_CFG1.
1236 switch(scsi_cfg1 & ADW_CABLE_DETECT) {
1259 scsi_cfg1 &= ~ADW_TERM_CTL;
1263 * set 'scsi_cfg1'. The TERM_POL bit does not need to be
1267 scsi_cfg1 |= (ADW_TERM_CTL_SEL | (~cfg->termination & ADW_TERM_CTL));
1270 * Set SCSI_CFG1 Microcode Default Value
1273 * bits in the Microcode SCSI_CFG1 Register Value.
1275 * The microcode will set the SCSI_CFG1 register using this value
1279 ADW_FLTR_DISABLE | scsi_cfg1);
1302 u_int16_t scsi_cfg1;
1306 * Determine SCSI_CFG1 Microcode Default Value.
1308 * The microcode will set the SCSI_CFG1 register using this value
1312 /* Read current SCSI_CFG1 Register value. */
1313 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1);
1337 if (scsi_cfg1 & ADW_HVD) {
1347 * to be 'ored' into SCSI_CFG1.
1351 switch(scsi_cfg1 & ADW_C_DET_SE) {
1366 switch(scsi_cfg1 & ADW_C_DET_LVD) {
1381 scsi_cfg1 &= (~ADW_TERM_SE & ~ADW_TERM_LVD);
1384 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
1386 scsi_cfg1 |= (~cfg->termination & 0xF0);
1391 * in the Microcode SCSI_CFG1 Register Value.
1393 scsi_cfg1 &= (~ADW_BIG_ENDIAN & ~ADW_DIS_TERM_DRV &
1397 * Set SCSI_CFG1 Microcode Default Value
1400 * bits in the Microcode SCSI_CFG1 Register Value.
1402 * The microcode will set the SCSI_CFG1 register using this value
1405 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
1428 u_int16_t scsi_cfg1;
1432 * Determine SCSI_CFG1 Microcode Default Value.
1434 * The microcode will set the SCSI_CFG1 register using this value
1440 /* Read current SCSI_CFG1 Register value. */
1441 scsi_cfg1 = ADW_READ_WORD_REGISTER(iot, ioh, IOPW_SCSI_CFG1);
1460 if (scsi_cfg1 & ADW_HVD) {
1476 * ready to be 'ored' into SCSI_CFG1.
1480 switch(scsi_cfg1 & ADW_C_DET_SE) {
1505 scsi_cfg1 &= ~ADW_TERM_SE;
1508 * Invert the TERM_SE bits and then set 'scsi_cfg1'.
1510 scsi_cfg1 |= (~cfg->termination & ADW_TERM_SE);
1514 * modified termination control bits in the Microcode SCSI_CFG1
1517 scsi_cfg1 &= (~ADW_BIG_ENDIAN & ~ADW_DIS_TERM_DRV & ~ADW_TERM_POL);
1520 * Set SCSI_CFG1 Microcode Default Value
1523 * SCSI_CFG1 Register Value.
1525 * The microcode will set the SCSI_CFG1 register using this value
1528 ADW_WRITE_WORD_LRAM(iot, ioh, ADW_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
Indexes created Fri Oct 03 02:09:57 GMT 2025