Lines Matching refs:AR_WRITE
390 AR_WRITE(sc, AR7010_GPIO_OUT, reg);
398 AR_WRITE(sc, AR_GPIO_IN_OUT, reg);
416 AR_WRITE(sc, AR_GPIO_OE_OUT, reg);
441 AR_WRITE(sc, AR_GPIO_OUTPUT_MUX(mux), reg);
446 AR_WRITE(sc, AR_GPIO_OE_OUT, reg);
459 AR_WRITE(sc, AR_GPIO_INPUT_MUX2, reg);
718 AR_WRITE(sc, AR_RXDP, SIMPLEQ_FIRST(&rxq->head)->bf_daddr);
719 AR_WRITE(sc, AR_CR, AR_CR_RXE);
822 AR_WRITE(sc, AR_RXDP, nbf->bf_daddr);
949 AR_WRITE(sc, AR_RXDP, bf->bf_daddr);
954 AR_WRITE(sc, AR_CR, AR_CR_RXE);
1156 AR_WRITE(sc, AR_QTXDP(ATHN_QID_BEACON), bf->bf_daddr);
1179 AR_WRITE(sc, AR_Q_TXE, 1 << ATHN_QID_BEACON);
1287 AR_WRITE(sc, AR_RC, AR_RC_HOSTIF);
1288 AR_WRITE(sc, AR_RC, 0);
1293 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0);
1298 AR_WRITE(sc, AR_INTR_SYNC_CAUSE, sync);
1659 AR_WRITE(sc, AR_QTXDP(qid), bf->bf_daddr);
1670 AR_WRITE(sc, AR_Q_TXE, 1 << qid);
1690 AR_WRITE(sc, AR_PHY_MODE, reg);
1713 AR_WRITE(sc, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1731 AR_WRITE(sc, AR_PHY_RFBUS_REQ, 0);
1754 AR_WRITE(sc, AR_PHY_TURBO, phy);
1756 AR_WRITE(sc, AR_2040_MODE,
1760 AR_WRITE(sc, AR_GTXTO, SM(AR_GTXTO_TIMEOUT_LIMIT, 25));
1762 AR_WRITE(sc, AR_CST, SM(AR_CST_TIMEOUT_LIMIT, 15));
1780 AR_WRITE(sc, AR_PHY_TIMING3, reg);
1790 AR_WRITE(sc, AR_PHY_HALFGI, reg);
1810 AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
1819 AR_WRITE(sc, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1833 AR_WRITE(sc, AR_PHY_RX_CHAINMASK, 0x7);
1834 AR_WRITE(sc, AR_PHY_CAL_CHAINMASK, 0x7);
1837 AR_WRITE(sc, AR_PHY_RX_CHAINMASK, sc->sc_rxchainmask);
1838 AR_WRITE(sc, AR_PHY_CAL_CHAINMASK, sc->sc_rxchainmask);
1840 AR_WRITE(sc, AR_SELFGEN_MASK, sc->sc_txchainmask);
1849 AR_WRITE(sc, AR_PHY_RX_CHAINMASK, sc->sc_rxchainmask);
1850 AR_WRITE(sc, AR_PHY_CAL_CHAINMASK, sc->sc_rxchainmask);
1893 AR_WRITE(sc, AR_PHY_CCA(i), reg);
1897 AR_WRITE(sc, AR_PHY_EXT_CCA(i), reg);
1992 AR_WRITE(sc, AR_PHY_TIMING_CTRL4_0, reg);
2000 AR_WRITE(sc, AR_PHY_CALMODE, mode);
2081 AR_WRITE(sc, AR_PHY_TIMING_CTRL4(i), reg);
2132 AR_WRITE(sc, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), reg);
2187 AR_WRITE(sc, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), reg);
2204 AR_WRITE(sc, AR_PHY_POWER_TX_RATE1,
2209 AR_WRITE(sc, AR_PHY_POWER_TX_RATE2,
2214 AR_WRITE(sc, AR_PHY_POWER_TX_RATE3,
2219 AR_WRITE(sc, AR_PHY_POWER_TX_RATE4,
2225 AR_WRITE(sc, AR_PHY_POWER_TX_RATE5,
2230 AR_WRITE(sc, AR_PHY_POWER_TX_RATE6,
2235 AR_WRITE(sc, AR_PHY_POWER_TX_RATE7,
2240 AR_WRITE(sc, AR_PHY_POWER_TX_RATE8,
2245 AR_WRITE(sc, AR_PHY_POWER_TX_RATE9,
2274 AR_WRITE(sc, AR_PHY_TIMING7, mask[0]);
2275 AR_WRITE(sc, AR_PHY_TIMING9, mask[0]);
2277 AR_WRITE(sc, AR_PHY_TIMING8, mask[1]);
2278 AR_WRITE(sc, AR_PHY_TIMING10, mask[1]);
2280 AR_WRITE(sc, AR_PHY_PILOT_MASK_01_30, mask[2]);
2281 AR_WRITE(sc, AR_PHY_CHANNEL_MASK_01_30, mask[2]);
2283 AR_WRITE(sc, AR_PHY_PILOT_MASK_31_60, mask[3]);
2284 AR_WRITE(sc, AR_PHY_CHANNEL_MASK_31_60, mask[3]);
2298 AR_WRITE(sc, AR_PHY_BIN_MASK_1, reg);
2299 AR_WRITE(sc, AR_PHY_VIT_MASK2_M_46_61, reg);
2306 AR_WRITE(sc, AR_PHY_BIN_MASK_2, reg);
2307 AR_WRITE(sc, AR_PHY_VIT_MASK2_M_31_45, reg);
2315 AR_WRITE(sc, AR_PHY_BIN_MASK_3, reg);
2316 AR_WRITE(sc, AR_PHY_VIT_MASK2_M_16_30, reg);
2323 AR_WRITE(sc, AR_PHY_MASK_CTL, reg);
2324 AR_WRITE(sc, AR_PHY_VIT_MASK2_M_00_15, reg);
2330 AR_WRITE(sc, AR_PHY_BIN_MASK2_1, reg);
2331 AR_WRITE(sc, AR_PHY_VIT_MASK2_P_15_01, reg);
2337 AR_WRITE(sc, AR_PHY_BIN_MASK2_2, reg);
2338 AR_WRITE(sc, AR_PHY_VIT_MASK2_P_30_16, reg);
2344 AR_WRITE(sc, AR_PHY_BIN_MASK2_3, reg);
2345 AR_WRITE(sc, AR_PHY_VIT_MASK2_P_45_31, reg);
2352 AR_WRITE(sc, AR_PHY_BIN_MASK2_4, reg);
2353 AR_WRITE(sc, AR_PHY_VIT_MASK2_P_61_46, reg);
2367 AR_WRITE(sc, AR_PHY(0), 0x00000007);
2368 AR_WRITE(sc, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
2373 AR_WRITE(sc, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
2399 AR_WRITE(sc, ini->regs[i], val);
2415 AR_WRITE(sc, AR_PHY(68), 0x30002311);
2416 AR_WRITE(sc, AR_PHY_RF_CTL3, 0x0a020001);
2423 AR_WRITE(sc, ini->cmregs[i], ini->cmvals[i]);
2447 AR_WRITE(sc, ini->fastregs[i], pvals[i]);
2470 AR_WRITE(sc, AR_PCU_MISC_MODE2, reg);
2475 AR_WRITE(sc, AR_PHY(651), 0x11);
2706 AR_WRITE(sc, AR_PHY_DESIRED_SZ, reg);
2711 AR_WRITE(sc, AR_PHY_AGC_CTL1, reg);
2715 AR_WRITE(sc, AR_PHY_FIND_SIG, reg);
2729 AR_WRITE(sc, AR_PHY_SFCORR_LOW, reg);
2735 AR_WRITE(sc, AR_PHY_SFCORR, reg);
2742 AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg);
2758 AR_WRITE(sc, AR_PHY_SFCORR_LOW, reg);
2764 AR_WRITE(sc, AR_PHY_SFCORR, reg);
2771 AR_WRITE(sc, AR_PHY_SFCORR_EXT, reg);
2785 AR_WRITE(sc, AR_PHY_CCK_DETECT, reg);
2796 AR_WRITE(sc, AR_PHY_FIND_SIG, reg);
2807 AR_WRITE(sc, AR_PHY_TIMING5, reg);
Indexes created Tue Oct 21 19:09:51 GMT 2025