Cross Reference: /src/sys/dev/ic/arn5008.c

Lines Matching refs:RW
458 	reg = RW(reg, AR_GPIO_INPUT_MUX2_RFSILENT, 0);
1778 	reg = RW(reg, AR_PHY_TIMING3_DSC_EXP, exp);
1779 	reg = RW(reg, AR_PHY_TIMING3_DSC_MAN, man);
1788 	reg = RW(reg, AR_PHY_HALFGI_DSC_EXP, exp);
1789 	reg = RW(reg, AR_PHY_HALFGI_DSC_MAN, man);
1892 		reg = RW(reg, AR_PHY_MAXCCA_PWR, nf[i]);
1896 		reg = RW(reg, AR_PHY_EXT_MAXCCA_PWR, nf_ext[i]);
1991 	reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX, log);
2079 		reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, i_coff);
2080 		reg = RW(reg, AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, q_coff);
2130 		reg = RW(reg, AR_PHY_NEW_ADC_DC_GAIN_IGAIN, gain_mismatch_i);
2131 		reg = RW(reg, AR_PHY_NEW_ADC_DC_GAIN_QGAIN, gain_mismatch_q);
2183 		reg = RW(reg, AR_PHY_NEW_ADC_DC_GAIN_QDC,
2185 		reg = RW(reg, AR_PHY_NEW_ADC_DC_GAIN_IDC,
2705 	reg = RW(reg, AR_PHY_DESIRED_SZ_TOT_DES, high ? -62 : -55);
2709 	reg = RW(reg, AR_PHY_AGC_CTL1_COARSE_LOW, high ? -70 : -64);
2710 	reg = RW(reg, AR_PHY_AGC_CTL1_COARSE_HIGH, high ? -12 : -14);
2714 	reg = RW(reg, AR_PHY_FIND_SIG_FIRPWR, high ? -80 : -78);
2726 	reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 50);
2727 	reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 40);
2728 	reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 48);
2732 	reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 77);
2733 	reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 64);
2734 	reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 16);
2738 	reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 50);
2739 	reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 40);
2740 	reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 77);
2741 	reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 64);
2755 	reg = RW(reg, AR_PHY_SFCORR_LOW_M1_THRESH_LOW, 127);
2756 	reg = RW(reg, AR_PHY_SFCORR_LOW_M2_THRESH_LOW, 127);
2757 	reg = RW(reg, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW, 63);
2761 	reg = RW(reg, AR_PHY_SFCORR_M1_THRESH, 127);
2762 	reg = RW(reg, AR_PHY_SFCORR_M2_THRESH, 127);
2763 	reg = RW(reg, AR_PHY_SFCORR_M2COUNT_THR, 31);
2767 	reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH_LOW, 127);
2768 	reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH_LOW, 127);
2769 	reg = RW(reg, AR_PHY_SFCORR_EXT_M1_THRESH, 127);
2770 	reg = RW(reg, AR_PHY_SFCORR_EXT_M2_THRESH, 127);
2784 	reg = RW(reg, AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK, high ? 6 : 8);
2795 	reg = RW(reg, AR_PHY_FIND_SIG_FIRSTEP, level * 4);
2806 	reg = RW(reg, AR_PHY_TIMING5_CYCPWR_THR1, (level + 1) * 2);
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