Lines Matching refs:AR_WRITE
495 AR_WRITE(sc, AR_BSSMSKL, 0xffffffff);
496 AR_WRITE(sc, AR_BSSMSKU, 0xffff);
501 AR_WRITE(sc, AR_MCAST_FIL0, 0xffffffff);
502 AR_WRITE(sc, AR_MCAST_FIL1, 0xffffffff);
504 AR_WRITE(sc, AR_FILT_OFDM, 0);
505 AR_WRITE(sc, AR_FILT_CCK, 0);
506 AR_WRITE(sc, AR_MIBC, 0);
507 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
508 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
511 AR_WRITE(sc, AR_PHY_ERR_1, 0);
512 AR_WRITE(sc, AR_PHY_ERR_2, 0);
526 AR_WRITE(sc, AR_RX_FILTER, rfilt);
531 AR_WRITE(sc, AR_PHY_ERR, reg);
537 AR_WRITE(sc, AR_PHY_ERR, 0);
562 AR_WRITE(sc, AR_INTR_ASYNC_MASK, 0);
563 AR_WRITE(sc, AR_INTR_SYNC_MASK, 0);
589 AR_WRITE(sc, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
590 AR_WRITE(sc, AR_INTR_SYNC_MASK, sc->sc_isync);
670 AR_WRITE(sc, AR_RTC_FORCE_WAKE,
675 AR_WRITE(sc, AR_RC, AR_RC_AHB);
678 AR_WRITE(sc, AR_RTC_RESET, 0);
682 AR_WRITE(sc, AR_RC, 0);
683 AR_WRITE(sc, AR_RTC_RESET, 1);
705 AR_WRITE(sc, AR_RTC_FORCE_WAKE,
710 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0);
711 AR_WRITE(sc, AR_RC, AR_RC_HOSTIF |
714 AR_WRITE(sc, AR_RC, AR_RC_AHB);
716 AR_WRITE(sc, AR_RTC_RC, AR_RTC_RC_MAC_WARM |
720 AR_WRITE(sc, AR_RTC_RC, 0);
731 AR_WRITE(sc, AR_RC, 0);
779 AR_WRITE(sc, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
796 AR_WRITE(sc, AR_RTC_PLL_CONTROL2, 0x886666);
824 AR_WRITE(sc, AR_RTC_PLL_CONTROL, pll);
829 AR_WRITE(sc, 0x50050, 0x304);
833 AR_WRITE(sc, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
844 AR_WRITE(sc, serdes->regs[i], serdes->vals[i]);
860 AR_WRITE(sc, AR_WA, sc->sc_workaround);
862 AR_WRITE(sc, AR_WA, ATHN_PCIE_WAEN);
967 AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC);
968 AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC);
969 AR_WRITE(sc, AR_FILT_OFDM, 0);
970 AR_WRITE(sc, AR_FILT_CCK, 0);
1036 AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), 0);
1037 AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), 0);
1039 AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), 0);
1040 AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), 0);
1042 AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), 0);
1043 AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
1045 AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), 0);
1046 AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), 0);
1100 AR_WRITE(sc, AR_KEYTABLE_KEY0(micentry), LE_READ_4(&rxmic[0]));
1101 AR_WRITE(sc, AR_KEYTABLE_KEY1(micentry), LE_READ_2(&txmic[2]));
1103 AR_WRITE(sc, AR_KEYTABLE_KEY2(micentry), LE_READ_4(&rxmic[4]));
1104 AR_WRITE(sc, AR_KEYTABLE_KEY3(micentry), LE_READ_2(&txmic[0]));
1106 AR_WRITE(sc, AR_KEYTABLE_KEY4(micentry), LE_READ_4(&txmic[4]));
1107 AR_WRITE(sc, AR_KEYTABLE_TYPE(micentry), AR_KEYTABLE_TYPE_CLR);
1109 AR_WRITE(sc, AR_KEYTABLE_KEY0(entry), LE_READ_4(&key[ 0]));
1110 AR_WRITE(sc, AR_KEYTABLE_KEY1(entry), LE_READ_2(&key[ 4]));
1112 AR_WRITE(sc, AR_KEYTABLE_KEY2(entry), LE_READ_4(&key[ 6]));
1113 AR_WRITE(sc, AR_KEYTABLE_KEY3(entry), LE_READ_2(&key[10]));
1115 AR_WRITE(sc, AR_KEYTABLE_KEY4(entry), LE_READ_4(&key[12]));
1116 AR_WRITE(sc, AR_KEYTABLE_TYPE(entry), type);
1126 AR_WRITE(sc, AR_KEYTABLE_MAC0(entry), lo);
1127 AR_WRITE(sc, AR_KEYTABLE_MAC1(entry), hi | AR_KEYTABLE_VALID);
1195 AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg);
1209 AR_WRITE(sc, AR_GPIO_INPUT_MUX1, reg);
1224 AR_WRITE(sc, AR_BT_COEX_MODE,
1231 AR_WRITE(sc, AR_BT_COEX_WEIGHT,
1234 AR_WRITE(sc, AR_BT_COEX_MODE2,
1252 AR_WRITE(sc, AR_GPIO_PDPU, reg);
1273 AR_WRITE(sc, AR_BT_COEX_MODE,
1275 AR_WRITE(sc, AR_BT_COEX_WEIGHT, 0);
1276 AR_WRITE(sc, AR_BT_COEX_MODE2, 0);
1589 AR_WRITE(sc, AR_PHY_ERR_1, 0);
1590 AR_WRITE(sc, AR_PHY_ERR_2, 0);
1591 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
1592 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
1638 AR_WRITE(sc, AR_PHY_ERR_1, ani->ofdm_phy_err_base);
1639 AR_WRITE(sc, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
1642 AR_WRITE(sc, AR_PHY_ERR_2, ani->cck_phy_err_base);
1643 AR_WRITE(sc, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
1732 AR_WRITE(sc, AR_TXCFG, reg);
1737 AR_WRITE(sc, AR_RXCFG, reg);
1740 AR_WRITE(sc, AR_RXFIFO_CFG, 512);
1744 AR_WRITE(sc, AR_PCU_TXBUF_CTRL,
1747 AR_WRITE(sc, AR_PCU_TXBUF_CTRL,
1771 AR_WRITE(sc, AR_TXCFG, reg);
1780 AR_WRITE(sc, AR_CR, AR_CR_RXD);
1847 AR_WRITE(sc, AR_Q_TXD, 1 << qid);
1856 AR_WRITE(sc, AR_QUIET2,
1858 AR_WRITE(sc, AR_QUIET_PERIOD, 100);
1859 AR_WRITE(sc, AR_NEXT_QUIET_TIMER, tsflo);
1878 AR_WRITE(sc, AR_Q_TXD, 0);
1916 AR_WRITE(sc, AR_DRETRY_LIMIT(qid),
1920 AR_WRITE(sc, AR_QMISC(qid),
1922 AR_WRITE(sc, AR_DMISC(qid),
1936 AR_WRITE(sc, AR_DLCL_IFS(ATHN_QID_BEACON),
1959 AR_WRITE(sc, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);
1962 AR_WRITE(sc, AR_IMR_S0, 0x00ff0000);
1964 AR_WRITE(sc, AR_IMR_S1, 0x00df0000);
2000 AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU);
2001 AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU);
2002 AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU);
2010 AR_WRITE(sc, AR_RSSI_THR, reg);
2012 AR_WRITE(sc, AR_NEXT_DTIM,
2014 AR_WRITE(sc, AR_NEXT_TIM,
2018 AR_WRITE(sc, AR_SLEEP1,
2021 AR_WRITE(sc, AR_SLEEP2,
2024 AR_WRITE(sc, AR_TIM_PERIOD, intval * IEEE80211_DUR_TU);
2025 AR_WRITE(sc, AR_DTIM_PERIOD, dtim_period * intval * IEEE80211_DUR_TU);
2031 AR_WRITE(sc, AR_TSFOOR_THRESHOLD, 0x4240);
2047 AR_WRITE(sc, AR_NEXT_TBTT_TIMER, next_tbtt * IEEE80211_DUR_TU);
2048 AR_WRITE(sc, AR_NEXT_DMA_BEACON_ALERT,
2050 AR_WRITE(sc, AR_NEXT_CFP,
2053 AR_WRITE(sc, AR_BEACON_PERIOD, intval * IEEE80211_DUR_TU);
2054 AR_WRITE(sc, AR_DMA_BEACON_PERIOD, intval * IEEE80211_DUR_TU);
2055 AR_WRITE(sc, AR_SWBA_PERIOD, intval * IEEE80211_DUR_TU);
2056 AR_WRITE(sc, AR_NDP_PERIOD, intval * IEEE80211_DUR_TU);
2058 AR_WRITE(sc, AR_TIMER_MODE,
2076 AR_WRITE(sc, AR_STA_ID1, reg);
2085 AR_WRITE(sc, AR_STA_ID1, reg);
2094 AR_WRITE(sc, AR_STA_ID1, reg);
2105 AR_WRITE(sc, AR_BSS_ID0, LE_READ_4(&bssid[0]));
2106 AR_WRITE(sc, AR_BSS_ID1, LE_READ_2(&bssid[4]) |
2118 AR_WRITE(sc, AR_IMR, sc->sc_imask);
2124 AR_WRITE(sc, AR_IMR_S2, mask2);
2128 AR_WRITE(sc, AR_IER, AR_IER_ENABLE);
2130 AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, AR_INTR_MAC_IRQ);
2131 AR_WRITE(sc, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2133 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->sc_isync);
2134 AR_WRITE(sc, AR_INTR_SYNC_MASK, sc->sc_isync);
2142 AR_WRITE(sc, AR_IER, 0);
2145 AR_WRITE(sc, AR_INTR_ASYNC_ENABLE, 0);
2148 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, 0);
2151 AR_WRITE(sc, AR_IMR, 0);
2166 AR_WRITE(sc, AR_MIC_QOS_CONTROL, 0x100aa);
2167 AR_WRITE(sc, AR_MIC_QOS_SELECT, 0x3210);
2168 AR_WRITE(sc, AR_QOS_NO_ACK,
2172 AR_WRITE(sc, AR_TXOP_X, AR_TXOP_X_VAL);
2174 AR_WRITE(sc, AR_TXOP_0_3, 0xffffffff);
2175 AR_WRITE(sc, AR_TXOP_4_7, 0xffffffff);
2176 AR_WRITE(sc, AR_TXOP_8_11, 0xffffffff);
2177 AR_WRITE(sc, AR_TXOP_12_15, 0xffffffff);
2209 AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL,
2251 AR_WRITE(sc, AR9271_RESET_POWER_DOWN_CONTROL,
2257 AR_WRITE(sc, AR_TSF_L32, tsflo);
2258 AR_WRITE(sc, AR_TSF_U32, tsfhi);
2281 AR_WRITE(sc, AR_AES_MUTE_MASK1, reg);
2297 AR_WRITE(sc, AR_STA_ID0, LE_READ_4(&ic->ic_myaddr[0]));
2298 AR_WRITE(sc, AR_STA_ID1, LE_READ_2(&ic->ic_myaddr[4]) |
2303 AR_WRITE(sc, AR_BSSMSKL, 0xffffffff);
2304 AR_WRITE(sc, AR_BSSMSKU, 0xffff);
2307 AR_WRITE(sc, AR_DEF_ANTENNA, def_ant);
2309 AR_WRITE(sc, AR_BSS_ID0, 0);
2310 AR_WRITE(sc, AR_BSS_ID1, 0);
2312 AR_WRITE(sc, AR_ISR, 0xffffffff);
2314 AR_WRITE(sc, AR_RSSI_THR, SM(AR_RSSI_THR_BM_THR, 7));
2324 AR_WRITE(sc, AR_DQCUMASK(i), 1 << i);
2340 AR_WRITE(sc, AR_IMR, sc->sc_imask);
2342 AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff);
2346 AR_WRITE(sc, AR_INTR_SYNC_ENABLE, sc->sc_isync);
2347 AR_WRITE(sc, AR_INTR_SYNC_MASK, 0);
2349 AR_WRITE(sc, AR_INTR_PRIO_ASYNC_ENABLE, 0);
2350 AR_WRITE(sc, AR_INTR_PRIO_ASYNC_MASK, 0);
2351 AR_WRITE(sc, AR_INTR_PRIO_SYNC_ENABLE, 0);
2352 AR_WRITE(sc, AR_INTR_PRIO_SYNC_MASK, 0);
2368 AR_WRITE(sc, sc->sc_obs_off, 8);
2371 AR_WRITE(sc, AR_RIMT, SM(AR_RIMT_FIRST, 2000) | SM(AR_RIMT_LAST, 500));
2383 AR_WRITE(sc, AR_CFG_LED, cfg_led | AR_CFG_SCLK_32KHZ);
2387 AR_WRITE(sc, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
2389 AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2394 AR_WRITE(sc, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2546 AR_WRITE(sc, AR_RX_FILTER, reg);
2578 AR_WRITE(sc, AR_DLCL_IFS(qid),
2583 AR_WRITE(sc, AR_DCHNTIME(qid),
2588 AR_WRITE(sc, AR_DCHNTIME(qid), 0);
2625 AR_WRITE(sc, AR_D_GBL_IFS_SLOT, slot * athn_clock_rate(sc));
2753 AR_WRITE(sc, AR_MCAST_FIL0, lo);
2754 AR_WRITE(sc, AR_MCAST_FIL1, hi);
2966 AR_WRITE(sc, AR_INTR_SYNC_CAUSE, 0xffffffff);
2967 AR_WRITE(sc, AR_INTR_SYNC_MASK, 0);
2977 AR_WRITE(sc, AR_MIBC, AR_MIBC_FMC);
2978 AR_WRITE(sc, AR_MIBC, AR_MIBC_CMC);
2979 AR_WRITE(sc, AR_FILT_OFDM, 0);
2980 AR_WRITE(sc, AR_FILT_CCK, 0);
Indexes created Wed Oct 22 06:10:02 GMT 2025