Cross Reference: /src/sys/dev/ic/bcmgenet.c

Lines Matching defs:qid
429 genet_set_rxthresh(struct genet_softc *sc, int qid, int usecs, int count)
446 	WR4(sc, GENET_RX_DMA_MBUF_DONE_THRES(qid), count);
448 	val = RD4(sc, GENET_RX_DMA_RING_TIMEOUT(qid));
451 	WR4(sc, GENET_RX_DMA_RING_TIMEOUT(qid), val);
455 genet_set_txthresh(struct genet_softc *sc, int qid, int count)
462 	WR4(sc, GENET_TX_DMA_MBUF_DONE_THRES(qid), count);
466 genet_init_rings(struct genet_softc *sc, int qid)
477 	WR4(sc, GENET_TX_DMA_READ_PTR_LO(qid), 0);
478 	WR4(sc, GENET_TX_DMA_READ_PTR_HI(qid), 0);
479 	WR4(sc, GENET_TX_DMA_CONS_INDEX(qid), 0);
480 	WR4(sc, GENET_TX_DMA_PROD_INDEX(qid), 0);
481 	WR4(sc, GENET_TX_DMA_RING_BUF_SIZE(qid),
484 	WR4(sc, GENET_TX_DMA_START_ADDR_LO(qid), 0);
485 	WR4(sc, GENET_TX_DMA_START_ADDR_HI(qid), 0);
486 	WR4(sc, GENET_TX_DMA_END_ADDR_LO(qid),
488 	WR4(sc, GENET_TX_DMA_END_ADDR_HI(qid), 0);
489 	WR4(sc, GENET_TX_DMA_FLOW_PERIOD(qid), 0);
490 	WR4(sc, GENET_TX_DMA_WRITE_PTR_LO(qid), 0);
491 	WR4(sc, GENET_TX_DMA_WRITE_PTR_HI(qid), 0);
494 	genet_set_txthresh(sc, qid, 10);
496 	WR4(sc, GENET_TX_DMA_RING_CFG, __BIT(qid));	/* enable */
510 	WR4(sc, GENET_RX_DMA_WRITE_PTR_LO(qid), 0);
511 	WR4(sc, GENET_RX_DMA_WRITE_PTR_HI(qid), 0);
512 	WR4(sc, GENET_RX_DMA_PROD_INDEX(qid), 0);
513 	WR4(sc, GENET_RX_DMA_CONS_INDEX(qid), 0);
514 	WR4(sc, GENET_RX_DMA_RING_BUF_SIZE(qid),
517 	WR4(sc, GENET_RX_DMA_START_ADDR_LO(qid), 0);
518 	WR4(sc, GENET_RX_DMA_START_ADDR_HI(qid), 0);
519 	WR4(sc, GENET_RX_DMA_END_ADDR_LO(qid),
521 	WR4(sc, GENET_RX_DMA_END_ADDR_HI(qid), 0);
522 	WR4(sc, GENET_RX_DMA_XON_XOFF_THRES(qid),
525 	WR4(sc, GENET_RX_DMA_READ_PTR_LO(qid), 0);
526 	WR4(sc, GENET_RX_DMA_READ_PTR_HI(qid), 0);
532 	genet_set_rxthresh(sc, qid, 57, 10);
534 	WR4(sc, GENET_RX_DMA_RING_CFG, __BIT(qid));	/* enable */
701 genet_rxintr(struct genet_softc *sc, int qid)
709 	pidx = RD4(sc, GENET_RX_DMA_PROD_INDEX(qid)) & 0xffff;
786 		WR4(sc, GENET_RX_DMA_CONS_INDEX(qid), sc->sc_rx.cidx);
794 genet_txintr(struct genet_softc *sc, int qid)
799 	cidx = RD4(sc, GENET_TX_DMA_CONS_INDEX(qid)) & 0xffff;
827 	const int qid = GENET_DMA_DEFAULT_QUEUE;
832 	sc->sc_tx.queued = (RD4(sc, GENET_TX_DMA_PROD_INDEX(qid))
864 		WR4(sc, GENET_TX_DMA_PROD_INDEX(qid), sc->sc_tx.pidx);
997 genet_setup_dma(struct genet_softc *sc, int qid)
1041 genet_claim_rxring(struct genet_softc *sc, int qid)
1174 	const int qid = GENET_DMA_DEFAULT_QUEUE;
1177 	printf("TX CIDX = %08x\n", RD4(sc, GENET_TX_DMA_CONS_INDEX(qid)));
1179 	printf("TX PIDX = %08x\n", RD4(sc, GENET_TX_DMA_PROD_INDEX(qid)));
1182 	printf("RX CIDX = %08x\n", RD4(sc, GENET_RX_DMA_CONS_INDEX(qid)));
1184 	printf("RX PIDX = %08x\n", RD4(sc, GENET_RX_DMA_PROD_INDEX(qid)));
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