Lines Matching refs:WR4
89 #define WR4(sc, reg, val) \
98 WR4(sc, GENET_MDIO_CMD,
125 WR4(sc, GENET_MDIO_CMD,
167 WR4(sc, GENET_EXT_RGMII_OOB_CTRL, val);
172 WR4(sc, GENET_UMAC_CMD, val);
191 WR4(sc, GENET_TX_DESC_ADDRESS_LO(index), (uint32_t)paddr);
192 WR4(sc, GENET_TX_DESC_ADDRESS_HI(index), (uint32_t)(paddr >> 32));
193 WR4(sc, GENET_TX_DESC_STATUS(index), status);
261 WR4(sc, GENET_RX_DESC_ADDRESS_LO(index), (uint32_t)paddr);
262 WR4(sc, GENET_RX_DESC_ADDRESS_HI(index), (uint32_t)(paddr >> 32));
302 WR4(sc, GENET_INTRL2_CPU_CLEAR_MASK,
310 WR4(sc, GENET_INTRL2_CPU_SET_MASK, 0xffffffff);
311 WR4(sc, GENET_INTRL2_CPU_CLEAR, 0xffffffff);
333 WR4(sc, GENET_UMAC_MDF_ADDR0(n), addr0);
334 WR4(sc, GENET_UMAC_MDF_ADDR1(n), addr1);
384 WR4(sc, GENET_UMAC_CMD, cmd);
385 WR4(sc, GENET_UMAC_MDF_CTRL, mdf_ctrl);
397 WR4(sc, GENET_SYS_RBUF_FLUSH_CTRL, val);
401 WR4(sc, GENET_SYS_RBUF_FLUSH_CTRL, val);
404 WR4(sc, GENET_SYS_RBUF_FLUSH_CTRL, 0);
407 WR4(sc, GENET_UMAC_CMD, 0);
408 WR4(sc, GENET_UMAC_CMD,
411 WR4(sc, GENET_UMAC_CMD, 0);
413 WR4(sc, GENET_UMAC_MIB_CTRL, GENET_UMAC_MIB_RESET_RUNT |
415 WR4(sc, GENET_UMAC_MIB_CTRL, 0);
417 WR4(sc, GENET_UMAC_MAX_FRAME_LEN, 1536);
421 WR4(sc, GENET_RBUF_CTRL, val);
423 WR4(sc, GENET_RBUF_TBUF_SIZE_CTRL, 1);
446 WR4(sc, GENET_RX_DMA_MBUF_DONE_THRES(qid), count);
451 WR4(sc, GENET_RX_DMA_RING_TIMEOUT(qid), val);
462 WR4(sc, GENET_TX_DMA_MBUF_DONE_THRES(qid), count);
475 WR4(sc, GENET_TX_SCB_BURST_SIZE, 0x08);
477 WR4(sc, GENET_TX_DMA_READ_PTR_LO(qid), 0);
478 WR4(sc, GENET_TX_DMA_READ_PTR_HI(qid), 0);
479 WR4(sc, GENET_TX_DMA_CONS_INDEX(qid), 0);
480 WR4(sc, GENET_TX_DMA_PROD_INDEX(qid), 0);
481 WR4(sc, GENET_TX_DMA_RING_BUF_SIZE(qid),
484 WR4(sc, GENET_TX_DMA_START_ADDR_LO(qid), 0);
485 WR4(sc, GENET_TX_DMA_START_ADDR_HI(qid), 0);
486 WR4(sc, GENET_TX_DMA_END_ADDR_LO(qid),
488 WR4(sc, GENET_TX_DMA_END_ADDR_HI(qid), 0);
489 WR4(sc, GENET_TX_DMA_FLOW_PERIOD(qid), 0);
490 WR4(sc, GENET_TX_DMA_WRITE_PTR_LO(qid), 0);
491 WR4(sc, GENET_TX_DMA_WRITE_PTR_HI(qid), 0);
496 WR4(sc, GENET_TX_DMA_RING_CFG, __BIT(qid)); /* enable */
502 WR4(sc, GENET_TX_DMA_CTRL, val);
508 WR4(sc, GENET_RX_SCB_BURST_SIZE, 0x08);
510 WR4(sc, GENET_RX_DMA_WRITE_PTR_LO(qid), 0);
511 WR4(sc, GENET_RX_DMA_WRITE_PTR_HI(qid), 0);
512 WR4(sc, GENET_RX_DMA_PROD_INDEX(qid), 0);
513 WR4(sc, GENET_RX_DMA_CONS_INDEX(qid), 0);
514 WR4(sc, GENET_RX_DMA_RING_BUF_SIZE(qid),
517 WR4(sc, GENET_RX_DMA_START_ADDR_LO(qid), 0);
518 WR4(sc, GENET_RX_DMA_START_ADDR_HI(qid), 0);
519 WR4(sc, GENET_RX_DMA_END_ADDR_LO(qid),
521 WR4(sc, GENET_RX_DMA_END_ADDR_HI(qid), 0);
522 WR4(sc, GENET_RX_DMA_XON_XOFF_THRES(qid),
525 WR4(sc, GENET_RX_DMA_READ_PTR_LO(qid), 0);
526 WR4(sc, GENET_RX_DMA_READ_PTR_HI(qid), 0);
534 WR4(sc, GENET_RX_DMA_RING_CFG, __BIT(qid)); /* enable */
540 WR4(sc, GENET_RX_DMA_CTRL, val);
561 WR4(sc, GENET_SYS_PORT_CTRL,
564 WR4(sc, GENET_SYS_PORT_CTRL, 0);
569 WR4(sc, GENET_UMAC_MAC0, val);
571 WR4(sc, GENET_UMAC_MAC1, val);
584 WR4(sc, GENET_UMAC_CMD, val);
657 WR4(sc, GENET_UMAC_CMD, val);
662 WR4(sc, GENET_RX_DMA_CTRL, val);
667 WR4(sc, GENET_TX_DMA_CTRL, val);
670 WR4(sc, GENET_UMAC_TX_FLUSH, 1);
672 WR4(sc, GENET_UMAC_TX_FLUSH, 0);
677 WR4(sc, GENET_UMAC_CMD, val);
786 WR4(sc, GENET_RX_DMA_CONS_INDEX(qid), sc->sc_rx.cidx);
864 WR4(sc, GENET_TX_DMA_PROD_INDEX(qid), sc->sc_tx.pidx);
885 WR4(sc, GENET_INTRL2_CPU_CLEAR, val);