Cross Reference: /src/sys/dev/ic/bwi.c

Lines Matching refs:CSR_READ_4
734 		intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS);
742 			intr_mask = CSR_READ_4(sc, BWI_MAC_INTR_MASK);
766 			    CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask;
809 				if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8)
1242 		return (CSR_READ_4(sc, BWI_MOBJ_DATA));
1290 		CSR_READ_4(mac->mac_sc, BWI_STATE_HI); /* dummy read */
1516 	state_lo = CSR_READ_4(sc, BWI_STATE_LO);
1522 	CSR_READ_4(sc, BWI_STATE_LO);
1528 	CSR_READ_4(sc, BWI_STATE_LO);
1533 	status = CSR_READ_4(sc, BWI_MAC_STATUS);
1619 	val = CSR_READ_4(sc, BWI_MAC_STATUS);
1626 	val = CSR_READ_4(sc, BWI_MAC_INTR_STATUS);
1767 	CSR_READ_4(sc, BWI_MAC_STATUS);	/* dummy read */
2124 		intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS);
2136 	CSR_READ_4(sc, BWI_MAC_INTR_STATUS);	/* dummy read */
2329 	mac_status = CSR_READ_4(sc, BWI_MAC_STATUS);
2514 	CSR_READ_4(sc, BWI_MAC_STATUS);
2515 	CSR_READ_4(sc, BWI_MAC_INTR_STATUS);
2533 	CSR_READ_4(sc, BWI_MAC_STATUS);
2537 		if (CSR_READ_4(sc, BWI_MAC_INTR_STATUS) & BWI_INTR_READY)
2556 	status = CSR_READ_4(sc, BWI_MAC_STATUS);
2563 	CSR_READ_4(sc, BWI_MAC_STATUS);
2628 	val = CSR_READ_4(sc, BWI_MAC_STATUS);
2633 		val = CSR_READ_4(sc, BWI_MAC_STATUS);
2645 	val = CSR_READ_4(sc, BWI_STATE_HI);
2655 		if (CSR_READ_4(sc, txrx_reg) & BWI_TXRX32_CTRL_ADDRHI_MASK) {
2998 	CSR_READ_4(sc, BWI_MAC_STATUS);
3159 	CSR_READ_4(mac->mac_sc, BWI_MAC_STATUS);
6619 	val = CSR_READ_4(sc, BWI_ID_HI);
6864 		info = CSR_READ_4(sc, BWI_INFO);
6869 		sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY);
7004 		val = CSR_READ_4(sc, BWI_FLAGS);
7063 			CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */
7065 			CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */
7144 		val = CSR_READ_4(sc, BWI_CLOCK_CTRL);
7157 		val = CSR_READ_4(sc, BWI_CLOCK_INFO);
7205 	clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL);
7328 			if ((CSR_READ_4(sc, BWI_TXSTATUS_0) &
7331 			CSR_READ_4(sc, BWI_TXSTATUS_1);
7669 		CSR_READ_4(sc, BWI_MAC_INTR_MASK);
7855 	ctl = CSR_READ_4(sc, BWI_PIO_TXCTL(idx));
8507 	val = CSR_READ_4(sc, ctrl_base + BWI_RX32_CTRL);
9073 	val = CSR_READ_4(sc, BWI_PIO_RXCTL(qid));
9082 		val = CSR_READ_4(sc, BWI_PIO_RXCTL(qid));
9143 	val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
9173 		status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
9243 		val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
9258 		val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
9904 	val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS);
10015 		tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS_0);
10018 		(void)CSR_READ_4(sc, BWI_TXSTATUS_1);
10072 	val = CSR_READ_4(sc, BWI_PLL_ON_DELAY);
10124 	busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK);
10142 	val = CSR_READ_4(sc, BWI_STATE_LO);
10163 	state_lo = CSR_READ_4(sc, BWI_STATE_LO);
10187 		state_lo = CSR_READ_4(sc, BWI_STATE_LO);
10200 		state_hi = CSR_READ_4(sc, BWI_STATE_HI);
10220 	CSR_READ_4(sc, BWI_STATE_LO);
10229 	CSR_READ_4(sc, BWI_STATE_LO);
10248 	CSR_READ_4(sc, BWI_STATE_LO);
10251 	state_hi = CSR_READ_4(sc, BWI_STATE_HI);
10255 	imstate = CSR_READ_4(sc, BWI_IMSTATE);
10268 	CSR_READ_4(sc, BWI_STATE_LO);
10277 	CSR_READ_4(sc, BWI_STATE_LO);
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