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Lines Matching refs:CSR_SETBITS_4

1356 		CSR_SETBITS_4(sc, BWI_CONF_LO,
1443 	CSR_SETBITS_4(sc, BWI_STATE_LO, 0x100000);
2319 	CSR_SETBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_INFRA);
2320 	CSR_SETBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN);
2510 	CSR_SETBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_ENABLE);
2995 	CSR_SETBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_RFLOCK);
3033 		CSR_SETBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PROMISC);
7010 		CSR_SETBITS_4(sc, BWI_INTRVEC, (val & BWI_FLAGS_INTR_MASK));
7032 		CSR_SETBITS_4(sc, BWI_BUS_CONFIG,
7045 			CSR_SETBITS_4(sc, BWI_CONF_LO,
7076 			CSR_SETBITS_4(sc, BWI_BUS_CONFIG, BWI_BUS_CONFIG_MRM);
8484 	CSR_SETBITS_4(sc, BWI_MAC_INTR_MASK, enable_intrs);