Cross Reference: /src/sys/dev/ic/bwi.c

Lines Matching refs:CSR_WRITE_2
813 			CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2);
1261 	CSR_WRITE_2(sc, data_reg, v);
1274 		CSR_WRITE_2(sc, BWI_MOBJ_DATA_UNALIGN, v >> 16);
1277 		CSR_WRITE_2(sc, BWI_MOBJ_DATA, v & 0xffff);
1321 	CSR_WRITE_2(mac->mac_sc, BWI_BBP_ATTEN, BWI_BBP_ATTEN_MAGIC);
1402 	CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0);
1419 		CSR_WRITE_2(sc, 0x60e, 0);
1420 		CSR_WRITE_2(sc, 0x610, 0x8000);
1421 		CSR_WRITE_2(sc, 0x604, 0);
1422 		CSR_WRITE_2(sc, 0x606, 0x200);
1446 	CSR_WRITE_2(sc, BWI_MAC_POWERUP_DELAY, sc->sc_pwron_delay);
1495 	CSR_WRITE_2(sc, 0x612, 0x50);	/* Force Pre-TBTT to 80? */
1531 	CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0);
1769 	CSR_WRITE_2(sc, 0x568, 0);
1770 	CSR_WRITE_2(sc, 0x7c0, 0);
1771 	CSR_WRITE_2(sc, 0x50c, val_50c);
1772 	CSR_WRITE_2(sc, 0x508, 0);
1773 	CSR_WRITE_2(sc, 0x50a, 0);
1774 	CSR_WRITE_2(sc, 0x54c, 0);
1775 	CSR_WRITE_2(sc, 0x56a, 0x14);
1776 	CSR_WRITE_2(sc, 0x568, 0x826);
1777 	CSR_WRITE_2(sc, 0x500, 0);
1778 	CSR_WRITE_2(sc, 0x502, 0x30);
2274 			CSR_WRITE_2(sc, ofs, val16);
2376 	CSR_WRITE_2(sc, BWI_MAC_PRE_TBTT, pre_tbtt);
2612 	CSR_WRITE_2(sc, BWI_BBP_ATTEN, BWI_BBP_ATTEN_MAGIC);
2689 	CSR_WRITE_2(mac->mac_sc, BWI_MAC_SLOTTIME,
3046 	CSR_WRITE_2(sc, BWI_PHY_CTRL, ctrl);
3047 	CSR_WRITE_2(sc, BWI_PHY_DATA, data);
3056 	CSR_WRITE_2(sc, BWI_PHY_CTRL, ctrl);
3351 	CSR_WRITE_2(sc, BWI_BPHY_CTRL, BWI_BPHY_CTRL_INIT);
3361 	CSR_WRITE_2(sc, BWI_PHY_MAGIC_REG1, BWI_PHY_MAGIC_REG1_VAL1);
3398 	CSR_WRITE_2(sc, BWI_RF_CHAN_EX, 0x1100);
3445 		CSR_WRITE_2(sc, BWI_RF_ANTDIV, 0);
3468 	CSR_WRITE_2(sc, BWI_BPHY_CTRL, BWI_BPHY_CTRL_INIT);
3476 		CSR_WRITE_2(sc, BWI_PHY_MAGIC_REG1, BWI_PHY_MAGIC_REG1_VAL1);
3627 		CSR_WRITE_2(sc, BWI_PHY_MAGIC_REG1, BWI_PHY_MAGIC_REG1_VAL2);
3634 		CSR_WRITE_2(sc, BWI_BBP_ATTEN, BWI_BBP_ATTEN_MAGIC2);
3647 		CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0);
3967 	CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl);
3968 	CSR_WRITE_2(sc, BWI_RF_DATA_LO, data);
3986 	CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl);
4017 		CSR_WRITE_2(sc, BWI_RF_CTRL, BWI_RF_CTRL_RFINFO);
4021 		CSR_WRITE_2(sc, BWI_RF_CTRL, BWI_RF_CTRL_RFINFO);
4120 	CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan));
4345 		CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan + 4));
4347 		CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(1));
4349 	CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan));
4550 		CSR_WRITE_2(sc, BWI_BPHY_CTRL, 0x3f3f);
4587 		CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x122);
4743 	CSR_WRITE_2(sc, BWI_BBP_ATTEN, bbp_atten);
4745 		CSR_WRITE_2(sc, BWI_RF_CHAN_EX, rf_chan_ex);
4752 		CSR_WRITE_2(sc, BWI_BPHY_CTRL, bphy_ctrl);
5059 	CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div | 0x8000);
5088 	CSR_WRITE_2(sc, BWI_RF_CHAN_EX, 0);
5136 	CSR_WRITE_2(sc, BWI_RF_CHAN_EX, chan_ex);
5150 	CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div);
5451 	CSR_WRITE_2(sc, BWI_BPHY_CTRL, 0x7f7f);
5465 		CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x40);
5467 		CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x122);
5491 	CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div);
5499 		CSR_WRITE_2(sc, BWI_RF_CHAN_EX, chan_ex);
5826 	CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div);
5827 	CSR_WRITE_2(sc, BWI_BBP_ATTEN, bbp_atten);
5828 	CSR_WRITE_2(sc, BWI_RF_CHAN_EX, chan_ex);
6375 		CSR_WRITE_2(sc, BWI_PHY_CTRL, 0x3f3f);
6452 		CSR_WRITE_2(sc, BWI_BPHY_CTRL, bphy_ctrl);
6758 	CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
6804 	CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
6825 	CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
8800 	CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL,
8808 		CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val);
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