Cross Reference: /src/sys/dev/ic/com.c

Lines Matching defs:CSR_WRITE_1
144 #define	CSR_WRITE_1(r, o, v)	\
518 	CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS);
519 	CSR_WRITE_1(regs, COM_REG_IIR, 0);
552 	CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier);
554 	CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr);
615 	CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
683 		CSR_WRITE_1(regsp, COM_REG_FIFO,
691 		CSR_WRITE_1(regsp, COM_REG_FIFO,
704 			CSR_WRITE_1(regsp, COM_REG_FIFO, 0);
708 			CSR_WRITE_1(regsp, COM_REG_FIFO,
719 		CSR_WRITE_1(regsp, COM_REG_FIFO,
727 		CSR_WRITE_1(regsp, COM_REG_FIFO,
731 		CSR_WRITE_1(regsp, COM_REG_FIFO,
756 				CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
757 				CSR_WRITE_1(regsp, COM_REG_EFR, 0);
759 					CSR_WRITE_1(regsp, COM_REG_LCR,
771 				CSR_WRITE_1(regsp, COM_REG_LCR, lcr);
794 				CSR_WRITE_1(regsp, COM_REG_LCR,
796 				CSR_WRITE_1(regsp, COM_REG_FIFO,
799 				CSR_WRITE_1(regsp, COM_REG_FIFO, fcr);
800 				CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB);
801 				CSR_WRITE_1(regsp, COM_REG_FIFO,
805 				CSR_WRITE_1(regsp, COM_REG_LCR, lcr);
813 					CSR_WRITE_1(regsp, COM_REG_FIFO, fcr);
824 	CSR_WRITE_1(regsp, COM_REG_FIFO, 0);
951 	CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
1100 	CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier);
1203 		CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier);
1906 		CSR_WRITE_1(regsp, COM_REG_FIFO,
1922 		CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART);
1924 		CSR_WRITE_1(regsp, COM_REG_IER, 0);
1928 		CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE);
1935 		CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
1936 		CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr);
1940 		CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
1941 		CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr | EFR_EFCR);
1948 		CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB);
1949 		CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl);
1950 		CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh);
1952 	CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr);
1953 	CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr);
1954 	CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo);
1957 		CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
1958 		CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr);
1959 		CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr);
1979 		CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR);
1982 		CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value);
1983 		CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value);
1986 		CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr);
1990 			CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X);
1992 			CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X);
1996 	CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
2063 	CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active);
2104 		CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
2273 				CSR_WRITE_1(&sc->sc_regs, COM_REG_IER,
2421 		CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr);
2431 			CSR_WRITE_1(regsp, COM_REG_HALT, HALT_CHCFG_EN);
2432 			CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB);
2433 			CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl);
2434 			CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh);
2435 			CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr);
2436 			CSR_WRITE_1(regsp, COM_REG_HALT,
2454 			CSR_WRITE_1(regsp, COM_REG_HALT, 0);
2457 			CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB);
2458 			CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl);
2459 			CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh);
2460 			CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr);
2567 				CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
2667 				CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
2769 	CSR_WRITE_1(regsp, COM_REG_TXDATA, c);
2789 		CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE);
2800 				CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
2801 				CSR_WRITE_1(regsp, COM_REG_EFR, 0);
2803 			CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB);
2804 			CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff);
2805 			CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8);
2808 	CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag));
2809 	CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS);
2812 		CSR_WRITE_1(regsp, COM_REG_FIFO,
2816 		CSR_WRITE_1(regsp, COM_REG_FIFO,
2833 		CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR);
2836 		CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value);
2837 		CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value);
2840 		CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS);
2844 			CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X);
2846 			CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X);
2851 		CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART);
2853 		CSR_WRITE_1(regsp, COM_REG_IER, 0);
3034 		CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0);
3044 	CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0);