Lines Matching defs:regsp
565 struct com_regs *regsp = &sc->sc_regs;
610 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
612 if ((bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) &&
613 regsp->cr_iobase == comcons_info.regs.cr_iobase) || force_console) {
617 memcpy(regsp, &comcons_info.regs, sizeof(*regsp));
678 CSR_WRITE_1(regsp, COM_REG_FIFO,
686 CSR_WRITE_1(regsp, COM_REG_FIFO,
699 CSR_WRITE_1(regsp, COM_REG_FIFO, 0);
703 CSR_WRITE_1(regsp, COM_REG_FIFO,
714 CSR_WRITE_1(regsp, COM_REG_FIFO,
722 CSR_WRITE_1(regsp, COM_REG_FIFO,
726 CSR_WRITE_1(regsp, COM_REG_FIFO,
729 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK)
731 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14)
750 lcr = CSR_READ_1(regsp, COM_REG_LCR);
751 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
752 CSR_WRITE_1(regsp, COM_REG_EFR, 0);
753 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) {
754 CSR_WRITE_1(regsp, COM_REG_LCR,
756 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) {
766 CSR_WRITE_1(regsp, COM_REG_LCR, lcr);
788 lcr = CSR_READ_1(regsp, COM_REG_LCR);
789 CSR_WRITE_1(regsp, COM_REG_LCR,
791 CSR_WRITE_1(regsp, COM_REG_FIFO,
793 iir1 = CSR_READ_1(regsp, COM_REG_IIR);
794 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr);
795 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB);
796 CSR_WRITE_1(regsp, COM_REG_FIFO,
798 iir2 = CSR_READ_1(regsp, COM_REG_IIR);
800 CSR_WRITE_1(regsp, COM_REG_LCR, lcr);
808 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr);
819 CSR_WRITE_1(regsp, COM_REG_FIFO, 0);
882 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) &&
883 regsp->cr_iobase == comkgdbregs.cr_iobase) {
939 struct com_regs *regsp = &sc->sc_regs;
946 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
947 (void) CSR_READ_1(regsp, COM_REG_IIR);
953 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1,
955 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
960 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1,
962 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
964 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
968 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1,
970 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
972 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
974 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
976 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
1862 struct com_regs *regsp = &sc->sc_regs;
1874 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)
1881 CSR_READ_1(regsp, COM_REG_RXDATA);
1895 fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 |
1897 CSR_WRITE_1(regsp, COM_REG_FIFO,
1907 struct com_regs *regsp = &sc->sc_regs;
1913 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART);
1915 CSR_WRITE_1(regsp, COM_REG_IER, 0);
1919 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE);
1926 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
1927 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr);
1931 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
1932 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr | EFR_EFCR);
1936 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl +
1939 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB);
1940 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl);
1941 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh);
1943 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr);
1944 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr);
1945 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo);
1948 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
1949 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr);
1950 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr);
1953 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1,
1955 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
1970 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR);
1973 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value);
1974 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value);
1977 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr);
1981 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X);
1983 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X);
1987 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
2042 struct com_regs *regsp= &sc->sc_regs;
2054 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active);
2063 struct com_regs *regsp = &sc->sc_regs;
2095 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
2105 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n);
2370 struct com_regs *regsp = &sc->sc_regs;
2379 KASSERT(regsp != NULL);
2382 iir = CSR_READ_1(regsp, COM_REG_IIR);
2388 (CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0; timeout--)
2397 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr);
2398 iir = CSR_READ_1(regsp, COM_REG_IIR);
2405 (void)CSR_READ_1(regsp, COM_REG_USR);
2406 } else if ((CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0) {
2407 CSR_WRITE_1(regsp, COM_REG_HALT, HALT_CHCFG_EN);
2408 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB);
2409 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl);
2410 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh);
2411 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr);
2412 CSR_WRITE_1(regsp, COM_REG_HALT,
2415 (CSR_READ_1(regsp, COM_REG_HALT) & HALT_CHCFG_UD) != 0;
2421 CSR_READ_1(regsp, COM_REG_HALT),
2422 CSR_READ_1(regsp, COM_REG_USR));
2426 CSR_WRITE_1(regsp, COM_REG_HALT, 0);
2427 (void)CSR_READ_1(regsp, COM_REG_USR);
2429 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB);
2430 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl);
2431 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh);
2432 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr);
2450 lsr = CSR_READ_1(regsp, COM_REG_LSR);
2473 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA);
2484 lsr = CSR_READ_1(regsp, COM_REG_LSR);
2529 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
2533 (void) CSR_READ_1(regsp, COM_REG_RXDATA);
2538 msr = CSR_READ_1(regsp, COM_REG_MSR);
2574 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) &&
2587 lsr = CSR_READ_1(regsp, COM_REG_LSR);
2613 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n);
2620 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
2629 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND))
2663 com_common_getc(dev_t dev, struct com_regs *regsp)
2682 if (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) {
2687 c = CSR_READ_1(regsp, COM_REG_RXDATA);
2688 stat = CSR_READ_1(regsp, COM_REG_IIR);
2699 com_common_putc(dev_t dev, struct com_regs *regsp, int c, int with_readahead)
2705 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) {
2707 cin = CSR_READ_1(regsp, COM_REG_RXDATA);
2708 stat = CSR_READ_1(regsp, COM_REG_IIR);
2715 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo)
2718 CSR_WRITE_1(regsp, COM_REG_TXDATA, c);
2719 COM_BARRIER(regsp, BR | BW);
2728 cominit(struct com_regs *regsp, int rate, int frequency, int type,
2732 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0,
2733 ®sp->cr_ioh))
2738 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE);
2745 CSR_WRITE_2(regsp, COM_REG_DLBL, rate);
2749 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
2750 CSR_WRITE_1(regsp, COM_REG_EFR, 0);
2752 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB);
2753 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff);
2754 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8);
2757 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag));
2758 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS);
2761 CSR_WRITE_1(regsp, COM_REG_FIFO,
2765 CSR_WRITE_1(regsp, COM_REG_FIFO,
2782 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR);
2785 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value);
2786 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value);
2789 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS);
2793 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X);
2795 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X);
2800 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART);
2802 CSR_WRITE_1(regsp, COM_REG_IER, 0);
2808 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type,
2813 comcons_info.regs = *regsp;
2884 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type,
2889 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) &&
2890 regsp->cr_iobase == comcons_info.regs.cr_iobase) {
2894 comkgdbregs = *regsp;
2898 comkgdbregs = *regsp;