Lines Matching defs:CSR_WRITE_1
139 #define CSR_WRITE_1(r, o, v) \
483 CSR_WRITE_1(regs, COM_REG_LCR, LCR_8BITS);
484 CSR_WRITE_1(regs, COM_REG_IIR, 0);
517 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier);
519 CSR_WRITE_1(&sc->sc_regs, COM_REG_MCR, sc->sc_mcr);
572 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
640 CSR_WRITE_1(regsp, COM_REG_FIFO,
648 CSR_WRITE_1(regsp, COM_REG_FIFO,
661 CSR_WRITE_1(regsp, COM_REG_FIFO, 0);
665 CSR_WRITE_1(regsp, COM_REG_FIFO,
674 CSR_WRITE_1(regsp, COM_REG_FIFO,
678 CSR_WRITE_1(regsp, COM_REG_FIFO,
703 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
704 CSR_WRITE_1(regsp, COM_REG_EFR, 0);
706 CSR_WRITE_1(regsp, COM_REG_LCR,
718 CSR_WRITE_1(regsp, COM_REG_LCR, lcr);
741 CSR_WRITE_1(regsp, COM_REG_LCR,
743 CSR_WRITE_1(regsp, COM_REG_FIFO,
746 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr);
747 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB);
748 CSR_WRITE_1(regsp, COM_REG_FIFO,
752 CSR_WRITE_1(regsp, COM_REG_LCR, lcr);
760 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr);
771 CSR_WRITE_1(regsp, COM_REG_FIFO, 0);
870 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
1010 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier);
1108 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, sc->sc_ier);
1795 CSR_WRITE_1(regsp, COM_REG_FIFO,
1811 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART);
1813 CSR_WRITE_1(regsp, COM_REG_IER, 0);
1817 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE);
1824 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
1825 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr);
1832 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB);
1833 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl);
1834 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh);
1836 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr);
1837 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr);
1838 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo);
1857 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR);
1860 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value);
1861 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value);
1864 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr);
1868 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X);
1870 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X);
1874 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
1929 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active);
1970 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
2120 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER,
2236 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr);
2246 CSR_WRITE_1(regsp, COM_REG_HALT, HALT_CHCFG_EN);
2247 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB);
2248 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl);
2249 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh);
2250 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr);
2251 CSR_WRITE_1(regsp, COM_REG_HALT,
2265 CSR_WRITE_1(regsp, COM_REG_HALT, 0);
2268 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB);
2269 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl);
2270 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh);
2271 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr);
2368 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
2459 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
2553 CSR_WRITE_1(regsp, COM_REG_TXDATA, c);
2573 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE);
2584 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
2585 CSR_WRITE_1(regsp, COM_REG_EFR, 0);
2587 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB);
2588 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff);
2589 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8);
2592 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag));
2593 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS);
2596 CSR_WRITE_1(regsp, COM_REG_FIFO,
2600 CSR_WRITE_1(regsp, COM_REG_FIFO,
2617 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR);
2620 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value);
2621 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value);
2624 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS);
2628 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X);
2630 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X);
2635 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART);
2637 CSR_WRITE_1(regsp, COM_REG_IER, 0);
2818 CSR_WRITE_1(&sc->sc_regs, COM_REG_FIFO, 0);
2828 CSR_WRITE_1(&sc->sc_regs, COM_REG_IER, 0);
Indexes created Wed Oct 01 15:09:59 GMT 2025