Lines Matching defs:regsp
535 struct com_regs *regsp = &sc->sc_regs;
572 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
574 if ((bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) &&
575 regsp->cr_iobase == comcons_info.regs.cr_iobase) || force_console) {
579 memcpy(regsp, &comcons_info.regs, sizeof(*regsp));
640 CSR_WRITE_1(regsp, COM_REG_FIFO,
648 CSR_WRITE_1(regsp, COM_REG_FIFO,
661 CSR_WRITE_1(regsp, COM_REG_FIFO, 0);
665 CSR_WRITE_1(regsp, COM_REG_FIFO,
674 CSR_WRITE_1(regsp, COM_REG_FIFO,
678 CSR_WRITE_1(regsp, COM_REG_FIFO,
681 if (ISSET(CSR_READ_1(regsp, COM_REG_IIR), IIR_FIFO_MASK)
683 if (ISSET(CSR_READ_1(regsp, COM_REG_FIFO), FIFO_TRIGGER_14)
702 lcr = CSR_READ_1(regsp, COM_REG_LCR);
703 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
704 CSR_WRITE_1(regsp, COM_REG_EFR, 0);
705 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) {
706 CSR_WRITE_1(regsp, COM_REG_LCR,
708 if (CSR_READ_1(regsp, COM_REG_EFR) == 0) {
718 CSR_WRITE_1(regsp, COM_REG_LCR, lcr);
740 lcr = CSR_READ_1(regsp, COM_REG_LCR);
741 CSR_WRITE_1(regsp, COM_REG_LCR,
743 CSR_WRITE_1(regsp, COM_REG_FIFO,
745 iir1 = CSR_READ_1(regsp, COM_REG_IIR);
746 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr);
747 CSR_WRITE_1(regsp, COM_REG_LCR, lcr | LCR_DLAB);
748 CSR_WRITE_1(regsp, COM_REG_FIFO,
750 iir2 = CSR_READ_1(regsp, COM_REG_IIR);
752 CSR_WRITE_1(regsp, COM_REG_LCR, lcr);
760 CSR_WRITE_1(regsp, COM_REG_FIFO, fcr);
771 CSR_WRITE_1(regsp, COM_REG_FIFO, 0);
829 if (bus_space_is_equal(regsp->cr_iot, comkgdbregs.cr_iot) &&
830 regsp->cr_iobase == comkgdbregs.cr_iobase) {
863 struct com_regs *regsp = &sc->sc_regs;
870 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
871 (void) CSR_READ_1(regsp, COM_REG_IIR);
877 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1,
879 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
884 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1,
886 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
888 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
892 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1,
894 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
896 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
898 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
900 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
1760 struct com_regs *regsp = &sc->sc_regs;
1772 while (ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)
1779 CSR_READ_1(regsp, COM_REG_RXDATA);
1793 fifo = CSR_READ_1(regsp, COM_REG_FIFO) & (FIFO_TRIGGER_1 |
1795 CSR_WRITE_1(regsp, COM_REG_FIFO,
1805 struct com_regs *regsp = &sc->sc_regs;
1811 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART);
1813 CSR_WRITE_1(regsp, COM_REG_IER, 0);
1817 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE);
1824 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
1825 CSR_WRITE_1(regsp, COM_REG_EFR, sc->sc_efr);
1829 CSR_WRITE_2(regsp, COM_REG_DLBL, sc->sc_dlbl +
1832 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB);
1833 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl);
1834 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh);
1836 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr);
1837 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active = sc->sc_mcr);
1838 CSR_WRITE_1(regsp, COM_REG_FIFO, sc->sc_fifo);
1840 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD1,
1842 bus_space_write_1(regsp->cr_iot, sc->sc_hayespioh, HAYESP_CMD2,
1857 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr | MCR_TCR_TLR);
1860 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value);
1861 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value);
1864 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr);
1868 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X);
1870 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X);
1874 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
1917 struct com_regs *regsp= &sc->sc_regs;
1929 CSR_WRITE_1(regsp, COM_REG_MCR, sc->sc_mcr_active);
1938 struct com_regs *regsp = &sc->sc_regs;
1970 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
1980 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n);
2209 struct com_regs *regsp = &sc->sc_regs;
2218 KASSERT(regsp != NULL);
2221 iir = CSR_READ_1(regsp, COM_REG_IIR);
2227 (CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0; timeout--)
2236 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr);
2237 iir = CSR_READ_1(regsp, COM_REG_IIR);
2244 (void)CSR_READ_1(regsp, COM_REG_USR);
2245 } else if ((CSR_READ_1(regsp, COM_REG_USR) & 0x1) != 0) {
2246 CSR_WRITE_1(regsp, COM_REG_HALT, HALT_CHCFG_EN);
2247 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB);
2248 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl);
2249 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh);
2250 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr);
2251 CSR_WRITE_1(regsp, COM_REG_HALT,
2254 (CSR_READ_1(regsp, COM_REG_HALT) & HALT_CHCFG_UD) != 0;
2260 CSR_READ_1(regsp, COM_REG_HALT),
2261 CSR_READ_1(regsp, COM_REG_USR));
2265 CSR_WRITE_1(regsp, COM_REG_HALT, 0);
2266 (void)CSR_READ_1(regsp, COM_REG_USR);
2268 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr | LCR_DLAB);
2269 CSR_WRITE_1(regsp, COM_REG_DLBL, sc->sc_dlbl);
2270 CSR_WRITE_1(regsp, COM_REG_DLBH, sc->sc_dlbh);
2271 CSR_WRITE_1(regsp, COM_REG_LCR, sc->sc_lcr);
2289 lsr = CSR_READ_1(regsp, COM_REG_LSR);
2312 put[0] = CSR_READ_1(regsp, COM_REG_RXDATA);
2323 lsr = CSR_READ_1(regsp, COM_REG_LSR);
2368 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
2372 (void) CSR_READ_1(regsp, COM_REG_RXDATA);
2377 msr = CSR_READ_1(regsp, COM_REG_MSR);
2413 CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND) &&
2426 lsr = CSR_READ_1(regsp, COM_REG_LSR);
2452 CSR_WRITE_MULTI(regsp, COM_REG_TXDATA, sc->sc_tba, n);
2459 CSR_WRITE_1(regsp, COM_REG_IER, sc->sc_ier);
2468 if (!ISSET((iir = CSR_READ_1(regsp, COM_REG_IIR)), IIR_NOPEND))
2498 com_common_getc(dev_t dev, struct com_regs *regsp)
2517 if (!ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) {
2522 c = CSR_READ_1(regsp, COM_REG_RXDATA);
2523 stat = CSR_READ_1(regsp, COM_REG_IIR);
2534 com_common_putc(dev_t dev, struct com_regs *regsp, int c, int with_readahead)
2540 && ISSET(stat = CSR_READ_1(regsp, COM_REG_LSR), LSR_RXRDY)) {
2542 cin = CSR_READ_1(regsp, COM_REG_RXDATA);
2543 stat = CSR_READ_1(regsp, COM_REG_IIR);
2550 while (!ISSET(CSR_READ_1(regsp, COM_REG_LSR), LSR_TXRDY) && --timo)
2553 CSR_WRITE_1(regsp, COM_REG_TXDATA, c);
2554 COM_BARRIER(regsp, BR | BW);
2563 cominit(struct com_regs *regsp, int rate, int frequency, int type,
2567 if (bus_space_map(regsp->cr_iot, regsp->cr_iobase, regsp->cr_nports, 0,
2568 ®sp->cr_ioh))
2573 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_DISABLE);
2580 CSR_WRITE_2(regsp, COM_REG_DLBL, rate);
2584 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_EERS);
2585 CSR_WRITE_1(regsp, COM_REG_EFR, 0);
2587 CSR_WRITE_1(regsp, COM_REG_LCR, LCR_DLAB);
2588 CSR_WRITE_1(regsp, COM_REG_DLBL, rate & 0xff);
2589 CSR_WRITE_1(regsp, COM_REG_DLBH, rate >> 8);
2592 CSR_WRITE_1(regsp, COM_REG_LCR, cflag2lcr(cflag));
2593 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS);
2596 CSR_WRITE_1(regsp, COM_REG_FIFO,
2600 CSR_WRITE_1(regsp, COM_REG_FIFO,
2617 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS | MCR_TCR_TLR);
2620 CSR_WRITE_1(regsp, COM_REG_TLR, tlr_value);
2621 CSR_WRITE_1(regsp, COM_REG_TCR, tcr_value);
2624 CSR_WRITE_1(regsp, COM_REG_MCR, MCR_DTR | MCR_RTS);
2628 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_13X);
2630 CSR_WRITE_1(regsp, COM_REG_MDR1, MDR1_MODE_UART_16X);
2635 CSR_WRITE_1(regsp, COM_REG_IER, IER_EUART);
2637 CSR_WRITE_1(regsp, COM_REG_IER, 0);
2643 comcnattach1(struct com_regs *regsp, int rate, int frequency, int type,
2648 comcons_info.regs = *regsp;
2719 com_kgdb_attach1(struct com_regs *regsp, int rate, int frequency, int type,
2724 if (bus_space_is_equal(regsp->cr_iot, comcons_info.regs.cr_iot) &&
2725 regsp->cr_iobase == comcons_info.regs.cr_iobase) {
2729 comkgdbregs = *regsp;
2733 comkgdbregs = *regsp;
Indexes created Wed Oct 01 19:09:53 GMT 2025