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Lines Matching refs:RD4

115 #define	RD4(sc, reg)			\
145 		addr = RD4(sc, GMAC_MAC_MDIO_ADDRESS);
147 			*val = RD4(sc, GMAC_MAC_MDIO_DATA) & 0xFFFF;
179 		addr = RD4(sc, GMAC_MAC_MDIO_ADDRESS);
203 	conf = RD4(sc, GMAC_MAC_CONFIGURATION);
491 	pfil = RD4(sc, GMAC_MAC_PACKET_FILTER);
559 		val = RD4(sc, GMAC_DMA_MODE);
623 	val = RD4(sc, GMAC_DMA_CHAN0_CONTROL);
628 	val = RD4(sc, GMAC_DMA_CHAN0_TX_CONTROL);
634 	val = RD4(sc, GMAC_DMA_CHAN0_RX_CONTROL);
663 	val = RD4(sc, GMAC_MTL_TXQ0_OPERATION_MODE);
670 	val = RD4(sc, GMAC_MTL_RXQ0_OPERATION_MODE);
687 	val = RD4(sc, GMAC_MAC_CONFIGURATION);
744 	val = RD4(sc, GMAC_MAC_CONFIGURATION);
749 	val = RD4(sc, GMAC_DMA_CHAN0_RX_CONTROL);
754 	val = RD4(sc, GMAC_DMA_CHAN0_TX_CONTROL);
760 		val = RD4(sc, GMAC_MTL_TXQ0_OPERATION_MODE);
765 			val = RD4(sc, GMAC_MTL_TXQ0_OPERATION_MODE);
778 	val = RD4(sc, GMAC_MAC_CONFIGURATION);
1066 		    RD4(sc, GMAC_DMA_CHAN0_CUR_TX_DESC),
1067 		    RD4(sc, GMAC_DMA_CHAN0_CUR_TX_BUF_ADDR));
1096 		debug_data = RD4(sc, GMAC_MTL_FIFO_DEBUG_DATA);
1102 		ictrl = RD4(sc, GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS);
1136 	mac_status = RD4(sc, GMAC_MAC_INTERRUPT_STATUS);
1137 	mac_status &= RD4(sc, GMAC_MAC_INTERRUPT_ENABLE);
1145 	mtl_status = RD4(sc, GMAC_MTL_INTERRUPT_STATUS);
1148 	dma_status = RD4(sc, GMAC_DMA_CHAN0_STATUS);
1149 	dma_status &= RD4(sc, GMAC_DMA_CHAN0_INTR_ENABLE);
1166 	rx_tx_status = RD4(sc, GMAC_MAC_RX_TX_STATUS);
1282 	maclo = RD4(sc, GMAC_MAC_ADDRESS0_LOW);
1283 	machi = RD4(sc, GMAC_MAC_ADDRESS0_HIGH) & 0xFFFF;
1328 	val = RD4(sc, GMAC_DMA_SYSBUS_MODE);
1486 	const uint32_t ver = RD4(sc, GMAC_MAC_VERSION);
1522 		sc->sc_hw_feature[n] = RD4(sc, GMAC_MAC_HW_FEATURE(n));
1783 	reg = RD4(sc, GMAC_DMA_CHAN0_CUR_TX_DESC);
1809 	reg = RD4(sc, GMAC_DMA_CHAN0_TX_END_ADDR);
1828 	reg = RD4(sc, GMAC_DMA_CHAN0_CUR_RX_DESC);
1847 	reg = RD4(sc, GMAC_DMA_CHAN0_RX_END_ADDR);