Cross Reference: /src/sys/dev/ic/dwc

Lines Matching refs:WR4
117 #define	WR4(sc, reg, val)		\
140 	WR4(sc, GMAC_MAC_MDIO_ADDRESS, addr);
168 	WR4(sc, GMAC_MAC_MDIO_DATA, val);
174 	WR4(sc, GMAC_MAC_MDIO_ADDRESS, addr);
229 	WR4(sc, GMAC_MAC_CONFIGURATION, conf);
237 	WR4(sc, GMAC_MAC_Q0_TX_FLOW_CTRL, flow);
244 	WR4(sc, GMAC_MAC_RX_FLOW_CTRL, flow);
438 	WR4(sc, GMAC_DMA_CHAN0_INTR_ENABLE,
450 	WR4(sc, GMAC_DMA_CHAN0_INTR_ENABLE, 0);
535 	WR4(sc, GMAC_MAC_ADDRESS0_HIGH, val);
538 	WR4(sc, GMAC_MAC_ADDRESS0_LOW, val);
541 	WR4(sc, GMAC_MAC_HASH_TABLE_REG0, hash[0]);
542 	WR4(sc, GMAC_MAC_HASH_TABLE_REG1, hash[1]);
547 	WR4(sc, GMAC_MAC_PACKET_FILTER, pfil);
556 	WR4(sc, GMAC_DMA_MODE, GMAC_DMA_MODE_SWR);
579 	WR4(sc, GMAC_DMA_CHAN0_TX_BASE_ADDR_HI,
581 	WR4(sc, GMAC_DMA_CHAN0_TX_BASE_ADDR,
583 	WR4(sc, GMAC_DMA_CHAN0_TX_RING_LEN, TX_DESC_COUNT - 1);
588 	WR4(sc, GMAC_DMA_CHAN0_RX_BASE_ADDR_HI,
590 	WR4(sc, GMAC_DMA_CHAN0_RX_BASE_ADDR,
592 	WR4(sc, GMAC_DMA_CHAN0_RX_RING_LEN, RX_DESC_COUNT - 1);
593 WR4(sc, GMAC_DMA_CHAN0_RX_END_ADDR,
620 	WR4(sc, GMAC_MAC_1US_TIC_COUNTER, (sc->sc_csr_clock / 1000000) - 1);
627 	WR4(sc, GMAC_DMA_CHAN0_CONTROL, val);
633 	WR4(sc, GMAC_DMA_CHAN0_TX_CONTROL, val);
640 	WR4(sc, GMAC_DMA_CHAN0_RX_CONTROL, val);
643 	WR4(sc, GMAC_MMC_CONTROL,
649 	WR4(sc, GMAC_MTL_TXQ0_OPERATION_MODE,
652 	WR4(sc, GMAC_MTL_RXQ0_OPERATION_MODE,
666 	WR4(sc, GMAC_MTL_TXQ0_OPERATION_MODE, val);
673 	WR4(sc, GMAC_MTL_RXQ0_OPERATION_MODE, val);
679 	WR4(sc, GMAC_MAC_Q0_TX_FLOW_CTRL, 0);
680 	WR4(sc, GMAC_MAC_RX_FLOW_CTRL, 0);
684 	WR4(sc, GMAC_RXQ_CTRL0, val);
694 	WR4(sc, GMAC_MAC_CONFIGURATION, val);
746 	WR4(sc, GMAC_MAC_CONFIGURATION, val);
751 	WR4(sc, GMAC_DMA_CHAN0_RX_CONTROL, val);
756 	WR4(sc, GMAC_DMA_CHAN0_TX_CONTROL, val);
762 		WR4(sc, GMAC_MTL_TXQ0_OPERATION_MODE, val);
780 	WR4(sc, GMAC_MAC_CONFIGURATION, val);
924 		WR4(sc, GMAC_DMA_CHAN0_RX_END_ADDR,
1068 		WR4(sc, GMAC_DMA_CHAN0_TX_END_ADDR,
1115 			WR4(sc, GMAC_MTL_Q0_INTERRUPT_CTRL_STATUS, new_status);
1151 		WR4(sc, GMAC_DMA_CHAN0_STATUS, dma_status);
1360 	WR4(sc, GMAC_DMA_SYSBUS_MODE, val);
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