Lines Matching refs:u_int16_t
247 #define GLOBAL_RESET (u_int16_t) 0x0000
248 #define WINDOW_SELECT (u_int16_t) (0x01<<11)
253 #define START_TRANSCEIVER (u_int16_t) (0x02<<11)
255 #define RX_DISABLE (u_int16_t) (0x03<<11)
256 #define RX_ENABLE (u_int16_t) (0x04<<11)
257 #define RX_RESET (u_int16_t) (0x05<<11)
258 #define RX_DISCARD_TOP_PACK (u_int16_t) (0x08<<11)
259 #define TX_ENABLE (u_int16_t) (0x09<<11)
260 #define TX_DISABLE (u_int16_t) (0x0a<<11)
261 #define TX_RESET (u_int16_t) (0x0b<<11)
262 #define REQ_INTR (u_int16_t) (0x0c<<11)
263 #define ACK_INTR (u_int16_t) (0x0d<<11)
264 #define SET_INTR_MASK (u_int16_t) (0x0e<<11)
266 #define STATUS_ENABLE (u_int16_t) (0x0f<<11)
267 #define SET_RD_0_MASK (u_int16_t) (0x0f<<11)
269 #define SET_RX_FILTER (u_int16_t) (0x10<<11)
270 # define FIL_INDIVIDUAL (u_int16_t) (0x01)
271 # define FIL_MULTICAST (u_int16_t) (0x02)
272 # define FIL_BRDCST (u_int16_t) (0x04)
273 # define FIL_PROMISC (u_int16_t) (0x08)
275 #define SET_RX_EARLY_THRESH (u_int16_t) (0x11<<11)
276 #define SET_TX_AVAIL_THRESH (u_int16_t) (0x12<<11)
277 #define SET_TX_START_THRESH (u_int16_t) (0x13<<11)
278 #define START_DMA (u_int16_t) (0x14<<11) /* busmaster-only */
281 #define STATS_ENABLE (u_int16_t) (0x15<<11)
282 #define STATS_DISABLE (u_int16_t) (0x16<<11)
283 #define STOP_TRANSCEIVER (u_int16_t) (0x17<<11)
286 #define POWERUP (u_int16_t) (0x1b<<11)
287 #define POWERDOWN (u_int16_t) (0x1c<<11)
288 #define POWERAUTO (u_int16_t) (0x1d<<11)
320 #define INTR_LATCH (u_int16_t) (0x0001)
321 #define CARD_FAILURE (u_int16_t) (0x0002)
322 #define TX_COMPLETE (u_int16_t) (0x0004)
323 #define TX_AVAIL (u_int16_t) (0x0008)
324 #define RX_COMPLETE (u_int16_t) (0x0010)
325 #define RX_EARLY (u_int16_t) (0x0020)
326 #define INT_RQD (u_int16_t) (0x0040)
327 #define UPD_STATS (u_int16_t) (0x0080)
328 #define DMA_DONE (u_int16_t) (0x0100) /* DMA cards only */
329 #define DMA_IN_PROGRESS (u_int16_t) (0x0800) /* DMA cards only */
330 #define COMMAND_IN_PROGRESS (u_int16_t) (0x1000)
353 #define ERR_INCOMPLETE (u_int16_t) (0x8000)
354 #define ERR_RX (u_int16_t) (0x4000)
355 #define ERR_MASK (u_int16_t) (0x7800)
356 #define ERR_OVERRUN (u_int16_t) (0x4000)
357 #define ERR_RUNT (u_int16_t) (0x5800)
358 #define ERR_ALIGNMENT (u_int16_t) (0x6000)
359 #define ERR_CRC (u_int16_t) (0x6800)
360 #define ERR_OVERSIZE (u_int16_t) (0x4800)
361 #define ERR_DRIBBLE (u_int16_t) (0x1000)
393 #define RX_BYTES_MASK (u_int16_t) (0x07ff)
414 #define CONFIG_RAMSIZE (u_int16_t) 0x0007
417 #define CONFIG_RAMWIDTH (u_int16_t) 0x0008
420 #define CONFIG_RAMSPEED (u_int16_t) 0x0030
422 #define CONFIG_ROMSIZE (u_int16_t) 0x00c0
426 #define CONFIG_RAMSPLIT (u_int16_t) 0x0003
428 #define CONFIG_MEDIAMASK (u_int16_t) 0x0070
431 #define CONFIG_AUTOSELECT (u_int16_t) 0x0100
442 #define ELINKMEDIA_10BASE_T (u_int16_t) 0x00
443 #define ELINKMEDIA_AUI (u_int16_t) 0x01
444 #define ELINKMEDIA_RESV1 (u_int16_t) 0x02
445 #define ELINKMEDIA_10BASE_2 (u_int16_t) 0x03
446 #define ELINKMEDIA_100BASE_TX (u_int16_t) 0x04
447 #define ELINKMEDIA_100BASE_FX (u_int16_t) 0x05
448 #define ELINKMEDIA_MII (u_int16_t) 0x06
449 #define ELINKMEDIA_100BASE_T4 (u_int16_t) 0x07
508 #define FIFOS_RX_RECEIVING (u_int16_t) 0x8000
509 #define FIFOS_RX_UNDERRUN (u_int16_t) 0x2000
510 #define FIFOS_RX_STATUS_OVERRUN (u_int16_t) 0x1000
511 #define FIFOS_RX_OVERRUN (u_int16_t) 0x0800
512 #define FIFOS_TX_OVERRUN (u_int16_t) 0x0400
Indexes created Sun Oct 19 02:09:48 GMT 2025