Lines Matching refs:ISP_WRITE
239 ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_HOST_INT);
240 ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RISC_INT);
241 ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_PAUSE);
243 ISP_WRITE(isp, HCCR, HCCR_CMD_PAUSE);
278 ISP_WRITE(isp, BIU2100_CSR, BIU2100_FPM0_REGS);
279 ISP_WRITE(isp, FPM_DIAG_CONFIG, FPM_SOFT_RESET);
280 ISP_WRITE(isp, BIU2100_CSR, BIU2100_FB_REGS);
281 ISP_WRITE(isp, FBM_CMD, FBMCMD_FIFO_RESET_ALL);
282 ISP_WRITE(isp, BIU2100_CSR, BIU2100_RISC_REGS);
474 ISP_WRITE(isp, BIU_ICR, BIU_ICR_SOFT_RESET);
483 ISP_WRITE(isp, CDMA_CONTROL, DMA_CNTRL_CLEAR_CHAN | DMA_CNTRL_RESET_INT);
484 ISP_WRITE(isp, DDMA_CONTROL, DMA_CNTRL_CLEAR_CHAN | DMA_CNTRL_RESET_INT);
491 ISP_WRITE(isp, BIU2400_CSR, BIU2400_DMA_STOP|(3 << 4));
507 ISP_WRITE(isp, BIU2400_CSR, BIU2400_SOFT_RESET|BIU2400_DMA_STOP|(3 << 4));
525 ISP_WRITE(isp, BIU2100_CSR, BIU2100_SOFT_RESET);
534 ISP_WRITE(isp, CDMA2100_CONTROL, DMA_CNTRL2100_CLEAR_CHAN | DMA_CNTRL2100_RESET_INT);
535 ISP_WRITE(isp, TDMA2100_CONTROL, DMA_CNTRL2100_CLEAR_CHAN | DMA_CNTRL2100_RESET_INT);
536 ISP_WRITE(isp, RDMA2100_CONTROL, DMA_CNTRL2100_CLEAR_CHAN | DMA_CNTRL2100_RESET_INT);
570 ISP_WRITE(isp, BIU_CONF1, 0);
572 ISP_WRITE(isp, BIU2100_CSR, 0);
579 ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_RESET);
580 ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_RELEASE);
581 ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RESET);
583 ISP_WRITE(isp, HCCR, HCCR_CMD_RESET);
585 ISP_WRITE(isp, BIU_SEMA, 0);
620 ISP_WRITE(isp, RISC_MTR, 0x1313);
621 ISP_WRITE(isp, HCCR, HCCR_CMD_STEP);
624 ISP_WRITE(isp, RISC_MTR, 0x1212);
629 ISP_WRITE(isp, RISC_EMB, DUAL_BANK);
631 ISP_WRITE(isp, RISC_MTR, 0x1212);
633 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE);
635 ISP_WRITE(isp, RISC_MTR2100, 0x1212);
637 ISP_WRITE(isp, HCCR, HCCR_2X00_DISABLE_PARITY_PAUSE);
639 ISP_WRITE(isp, HCCR, HCCR_CMD_RELEASE);
642 ISP_WRITE(isp, isp->isp_rqstinrp, 0);
643 ISP_WRITE(isp, isp->isp_rqstoutrp, 0);
644 ISP_WRITE(isp, isp->isp_respinrp, 0);
645 ISP_WRITE(isp, isp->isp_respoutrp, 0);
647 ISP_WRITE(isp, BIU2400_PRI_REQINP, 0);
648 ISP_WRITE(isp, BIU2400_PRI_REQOUTP, 0);
649 ISP_WRITE(isp, BIU2400_ATIO_RSPINP, 0);
650 ISP_WRITE(isp, BIU2400_ATIO_RSPOUTP, 0);
1199 ISP_WRITE(isp, RISC_MTR, 0x1313);
4920 ISP_WRITE(isp, isp->isp_respoutrp, ISP_READ(isp, isp->isp_respinrp));
4956 ISP_WRITE(isp, BIU2400_ATIO_RSPOUTP, optr);
5122 ISP_WRITE(isp, isp->isp_respoutrp, optr);
5157 ISP_WRITE(isp, isp->isp_respoutrp, optr);
5180 ISP_WRITE(isp, isp->isp_respoutrp, optr);
5188 ISP_WRITE(isp, isp->isp_respoutrp, optr);
5204 ISP_WRITE(isp, isp->isp_respoutrp, optr);
5364 ISP_WRITE(isp, isp->isp_respoutrp, optr);
5377 ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RISC_INT);
5379 ISP_WRITE(isp, HCCR, HCCR_CMD_CLEAR_RISC_INT);
5380 ISP_WRITE(isp, BIU_SEMA, 0);
6575 ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_CLEAR_RISC_INT);
6577 ISP_WRITE(isp, HCCR, HCCR_CMD_CLEAR_RISC_INT);
6578 ISP_WRITE(isp, BIU_SEMA, 0);
7107 ISP_WRITE(isp, MBOX_OFF(box), mbp->param[box]);
7119 ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_SET_HOST_INT);
7121 ISP_WRITE(isp, HCCR, HCCR_CMD_SET_HOST_INT);
7182 ISP_WRITE(isp, MBOX_OFF(box), mbp->param[box]);
7199 ISP_WRITE(isp, BIU2400_HCCR, HCCR_2400_CMD_SET_HOST_INT);
7201 ISP_WRITE(isp, HCCR, HCCR_CMD_SET_HOST_INT);
7677 ISP_WRITE(isp, BIU2100_CSR, BIU2100_FPM0_REGS);
7678 ISP_WRITE(isp, FPM_DIAG_CONFIG, FPM_SOFT_RESET);
7679 ISP_WRITE(isp, BIU2100_CSR, BIU2100_FB_REGS);
7680 ISP_WRITE(isp, FBM_CMD, FBMCMD_FIFO_RESET_ALL);
7681 ISP_WRITE(isp, BIU2100_CSR, BIU2100_RISC_REGS);
7819 ISP_WRITE(isp, BIU_NVRAM, BIU_NVRAM_SELECT);
7821 ISP_WRITE(isp, BIU_NVRAM, BIU_NVRAM_SELECT|BIU_NVRAM_CLOCK);
7850 ISP_WRITE(isp, BIU_NVRAM, bit);
7853 ISP_WRITE(isp, BIU_NVRAM, bit | BIU_NVRAM_CLOCK);
7856 ISP_WRITE(isp, BIU_NVRAM, bit);
7867 ISP_WRITE(isp, BIU_NVRAM, BIU_NVRAM_SELECT|BIU_NVRAM_CLOCK);
7874 ISP_WRITE(isp, BIU_NVRAM, BIU_NVRAM_SELECT);
7878 ISP_WRITE(isp, BIU_NVRAM, 0);
7894 ISP_WRITE(isp, BIU2400_FLASH_ADDR, base | addr);
Indexes created Wed Oct 22 13:09:56 GMT 2025