Lines Matching refs:SC
85 lsi64854_attach(struct lsi64854_softc *sc)
90 switch (sc->sc_channel) {
92 sc->intr = lsi64854_scsi_intr;
93 sc->setup = lsi64854_setup;
96 sc->intr = lsi64854_enet_intr;
99 sc->setup = lsi64854_setup_pp;
104 sc->reset = lsi64854_reset;
107 if (bus_dmamap_create(sc->sc_dmatag, MAX_DMA_SZ, 1, MAX_DMA_SZ,
108 0, BUS_DMA_WAITOK, &sc->sc_dmamap) != 0) {
113 csr = L64854_GCSR(sc);
114 sc->sc_rev = csr & L64854_DEVID;
115 if (sc->sc_rev == DMAREV_HME) {
119 switch (sc->sc_rev) {
136 aprint_normal("unknown (0x%x)", sc->sc_rev);
139 DPRINTF(LDB_ANY, (", burst 0x%x, csr 0x%x", sc->sc_burst, csr));
146 #define DMAWAIT(SC, COND, MSG, DONTPANIC) do if (COND) { \
151 (u_long)L64854_GCSR(SC)); \
159 #define DMA_DRAIN(sc, dontpanic) do { \
167 DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\
168 if (sc->sc_rev != DMAREV_HME) { \
173 _csr = L64854_GCSR(sc); \
174 if (sc->sc_rev == DMAREV_1 || sc->sc_rev == DMAREV_0) \
179 L64854_SCSR(sc,_csr); \
185 DMAWAIT(sc, L64854_GCSR(sc) & L64854_DRAINING, "DRAINING", dontpanic);\
188 #define DMA_FLUSH(sc, dontpanic) do { \
196 DMAWAIT(sc, L64854_GCSR(sc) & D_ESC_R_PEND, "R_PEND", dontpanic);\
197 _csr = L64854_GCSR(sc); \
200 L64854_SCSR(sc,_csr); \
204 lsi64854_reset(struct lsi64854_softc *sc)
208 DMA_FLUSH(sc, 1);
209 csr = L64854_GCSR(sc);
216 if (sc->sc_dmamap->dm_nsegs > 0)
217 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap);
219 if (sc->sc_rev == DMAREV_HME)
220 L64854_SCSR(sc, csr | D_HW_RESET_FAS366);
224 L64854_SCSR(sc, csr);
227 /*DMAWAIT1(sc); why was this here? */
228 csr = L64854_GCSR(sc);
230 L64854_SCSR(sc, csr);
233 csr = L64854_GCSR(sc);
235 if (sc->sc_rev > DMAREV_1 && sc->sc_channel == L64854_CHANNEL_SCSI) {
236 if (sc->sc_rev == DMAREV_HME)
243 switch (sc->sc_rev) {
247 if (sc->sc_burst == 32) {
249 } else if (sc->sc_burst == 16) {
257 if (sc->sc_burst == 32) {
265 L64854_SCSR(sc, csr);
267 if (sc->sc_rev == DMAREV_HME) {
268 bus_space_write_4(sc->sc_bustag, sc->sc_regs,
270 sc->sc_dmactl = csr;
272 sc->sc_active = 0;
283 lsi64854_setup(struct lsi64854_softc *sc, uint8_t **addr, size_t *len,
288 DMA_FLUSH(sc, 0);
291 DMACSR(sc) &= ~D_INT_EN;
293 sc->sc_dmaaddr = addr;
294 sc->sc_dmalen = len;
301 *dmasize = sc->sc_dmasize =
302 uimin(*dmasize, DMAMAX((size_t)*sc->sc_dmaaddr));
305 __func__, (long)sc->sc_dmasize));
310 if (sc->sc_rev == DMAREV_HME) {
312 L64854_SCSR(sc, sc->sc_dmactl | L64854_RESET);
313 L64854_SCSR(sc, sc->sc_dmactl);
315 bus_space_write_4(sc->sc_bustag, sc->sc_regs,
320 if (sc->sc_dmasize) {
321 sc->sc_dvmaaddr = *sc->sc_dmaaddr;
322 if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap,
323 *sc->sc_dmaaddr, sc->sc_dmasize,
327 device_xname(sc->sc_dev));
328 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize,
330 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR,
331 sc->sc_dmamap->dm_segs[0].ds_addr);
334 if (sc->sc_rev == DMAREV_ESC) {
336 long bcnt = sc->sc_dmasize;
337 long eaddr = bcnt + (long)*sc->sc_dmaaddr;
341 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT,
346 csr = L64854_GCSR(sc);
354 if (sc->sc_rev == DMAREV_HME) {
358 L64854_SCSR(sc, csr);
373 struct lsi64854_softc *sc = arg;
374 struct ncr53c9x_softc *nsc = sc->sc_client;
379 csr = L64854_GCSR(sc);
384 device_xname(sc->sc_dev), __func__,
385 bus_space_read_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR),
391 printf("%s: error: csr=%s\n", device_xname(sc->sc_dev), bits);
395 L64854_SCSR(sc, csr);
400 if (sc->sc_active == 0)
403 DMA_DRAIN(sc, 0);
407 L64854_SCSR(sc, csr);
408 sc->sc_active = 0;
410 if (sc->sc_dmasize == 0) {
447 if (resid == 0 && sc->sc_dmasize == 65536 &&
453 trans = sc->sc_dmasize - resid;
462 device_xname(sc->sc_dev), trans, sc->sc_dmasize);
464 trans = sc->sc_dmasize;
475 if (sc->sc_dmamap->dm_nsegs > 0) {
476 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize,
479 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap);
482 *sc->sc_dmalen -= trans;
483 *sc->sc_dmaaddr += trans;
486 if (*sc->sc_dmalen == 0 ||
491 dma_start(sc, sc->sc_dmaaddr, sc->sc_dmalen, DMACSR(sc) & D_WRITE);
503 struct lsi64854_softc *sc = arg;
509 csr = L64854_GCSR(sc);
516 printf("%s: error: csr=%s\n", device_xname(sc->sc_dev), bits);
520 L64854_SCSR(sc, csr);
521 DMA_RESET(sc);
529 L64854_SCSR(sc, csr);
530 while (i-- > 0 && (L64854_GCSR(sc) & D_DRAINING))
534 return rv | (*sc->sc_intrchain)(sc->sc_intrchainarg);
541 lsi64854_setup_pp(struct lsi64854_softc *sc, uint8_t **addr, size_t *len,
546 DMA_FLUSH(sc, 0);
548 sc->sc_dmaaddr = addr;
549 sc->sc_dmalen = len;
551 DPRINTF(LDB_PP, ("%s: pp start %ld@%p,%d\n", device_xname(sc->sc_dev),
552 (long)*sc->sc_dmalen, *sc->sc_dmaaddr, datain ? 1 : 0));
559 *dmasize = sc->sc_dmasize =
560 uimin(*dmasize, DMAMAX((size_t) *sc->sc_dmaaddr));
563 __func__, (long)sc->sc_dmasize));
566 if (sc->sc_dmasize) {
567 sc->sc_dvmaaddr = *sc->sc_dmaaddr;
568 if (bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap,
569 *sc->sc_dmaaddr, sc->sc_dmasize,
573 device_xname(sc->sc_dev));
574 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize,
576 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR,
577 sc->sc_dmamap->dm_segs[0].ds_addr);
579 bus_space_write_4(sc->sc_bustag, sc->sc_regs, L64854_REG_CNT,
580 sc->sc_dmasize);
584 csr = L64854_GCSR(sc);
586 if (sc->sc_burst == 32) {
588 } else if (sc->sc_burst == 16) {
601 L64854_SCSR(sc, csr);
611 struct lsi64854_softc *sc = arg;
616 csr = L64854_GCSR(sc);
622 device_xname(sc->sc_dev),
623 sc->sc_bustag, sc->sc_regs, L64854_REG_ADDR),
627 resid = bus_space_read_4(sc->sc_bustag, sc->sc_regs,
631 device_xname(sc->sc_dev), resid, bits);
635 L64854_SCSR(sc, csr);
641 if (sc->sc_active != 0) {
642 DMA_DRAIN(sc, 0);
643 resid = bus_space_read_4(sc->sc_bustag, sc->sc_regs,
649 L64854_SCSR(sc, csr);
650 sc->sc_active = 0;
652 trans = sc->sc_dmasize - resid;
654 trans = sc->sc_dmasize;
656 *sc->sc_dmalen -= trans;
657 *sc->sc_dmaaddr += trans;
659 if (sc->sc_dmamap->dm_nsegs > 0) {
660 bus_dmamap_sync(sc->sc_dmatag, sc->sc_dmamap, 0, sc->sc_dmasize,
663 bus_dmamap_unload(sc->sc_dmatag, sc->sc_dmamap);
Indexes created Thu Oct 16 14:10:15 GMT 2025