Cross Reference: /src/sys/dev/ic/ninjascsi32.c

Lines Matching defs:njsc32_write_2
173 njsc32_write_2(struct njsc32_softc *sc, int no, int val)
298 	njsc32_write_2(sc, NJSC32_REG_IRQ, NJSC32_IRQ_MASK_ALL);
301 	njsc32_write_2(sc, NJSC32_REG_TRANSFER, 0);
380 	njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_TIMER_STOP);
381 	njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_TIMER_STOP);
386 	njsc32_write_2(sc, NJSC32_REG_SEL_TIMEOUT,
564 	njsc32_write_2(sc, NJSC32_REG_TRANSFER, NJSC32_XFR_DUALEDGE_ENABLE);
574 	njsc32_write_2(sc, NJSC32_REG_TRANSFER, 0);	/* restore */
911 	njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, NJSC32_CMD_CLEAR_CDB_FIFO_PTR);
988 	njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL,
1002 	njsc32_write_2(sc, NJSC32_REG_TRANSFER,
1005 	njsc32_write_2(sc, NJSC32_REG_TRANSFER, cmd->c_xferctl);
1008 	njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL,
1058 	njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_ARBITRATION_RETRY_TIME);
1059 out:	njsc32_write_2(sc, NJSC32_REG_TRANSFER, 0);
1346 	njsc32_write_2(sc, NJSC32_REG_IRQ, 0);
1359 	njsc32_write_2(sc, NJSC32_REG_IRQ, NJSC32_IRQ_MASK_ALL);
1698 	njsc32_write_2(sc, NJSC32_REG_TRANSFER,
1701 	njsc32_write_2(sc, NJSC32_REG_TRANSFER, cmd->c_xferctl);
1704 	njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl);
2112 		njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl);
2152 		njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl);
2163 		njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, 0);
2180 	njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl);
2352 	njsc32_write_2(sc, NJSC32_REG_IRQ, NJSC32_IRQ_MASK_ALL);
2356 	njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_TIMER_STOP);
2508 		njsc32_write_2(sc, NJSC32_REG_EXECUTE_PHASE, 0);
2616 					njsc32_write_2(sc,
2702 	njsc32_write_2(sc, NJSC32_REG_IRQ, 0);
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