Lines Matching refs:sc
48 #define rtc_begin(sc) ((*sc->sc_ops->rs5c313_op_begin)(sc))
49 #define rtc_ce(sc, onoff) ((*sc->sc_ops->rs5c313_op_ce)(sc, onoff))
50 #define rtc_clk(sc, onoff) ((*sc->sc_ops->rs5c313_op_clk)(sc, onoff))
51 #define rtc_dir(sc, output) ((*sc->sc_ops->rs5c313_op_dir)(sc, output))
52 #define rtc_di(sc) ((*sc->sc_ops->rs5c313_op_read)(sc))
53 #define rtc_do(sc, bit) ((*sc->sc_ops->rs5c313_op_write)(sc, bit))
61 rs5c313_attach(struct rs5c313_softc *sc)
63 device_t self = sc->sc_dev;
66 switch (sc->sc_model) {
69 sc->sc_ctrl[0] = CTRL_24H;
70 sc->sc_ctrl[1] = CTRL2_NTEST;
75 sc->sc_ctrl[0] = 0;
76 sc->sc_ctrl[1] = CTRL2_24H|CTRL2_NTEST;
80 aprint_error("unknown model (%d)\n", sc->sc_model);
87 sc->sc_todr.todr_dev = self;
88 sc->sc_todr.todr_gettime_ymdhms = rs5c313_todr_gettime_ymdhms;
89 sc->sc_todr.todr_settime_ymdhms = rs5c313_todr_settime_ymdhms;
91 if (rs5c313_init(sc) != 0) {
96 todr_attach(&sc->sc_todr);
101 rs5c313_init(struct rs5c313_softc *sc)
103 device_t self = sc->sc_dev;
107 rtc_ce(sc, 0);
109 rtc_begin(sc);
110 rtc_ce(sc, 1);
112 if ((rs5c313_read_reg(sc, RS5C313_CTRL) & CTRL_XSTP) == 0) {
113 sc->sc_valid = 1;
117 sc->sc_valid = 0;
120 rs5c313_write_reg(sc, RS5C313_TINT, 0);
121 rs5c313_write_reg(sc, RS5C313_CTRL, (sc->sc_ctrl[0] | CTRL_ADJ));
124 if (rs5c313_read_reg(sc, RS5C313_CTRL) & CTRL_BSY)
134 rs5c313_write_reg(sc, RS5C313_CTRL, sc->sc_ctrl[0]);
135 rs5c313_write_reg(sc, RS5C313_CTRL2, sc->sc_ctrl[1]);
138 rtc_ce(sc, 0);
146 struct rs5c313_softc *sc = device_private(todr->todr_dev);
154 if (sc->sc_valid == 0)
159 rtc_begin(sc);
161 rtc_ce(sc, 1);
163 rs5c313_write_reg(sc, RS5C313_CTRL, sc->sc_ctrl[0]);
164 if ((rs5c313_read_reg(sc, RS5C313_CTRL) & CTRL_BSY) == 0)
167 rtc_ce(sc, 0);
177 int ones = rs5c313_read_reg(sc, RS5C313_ ## y ## 1); \
178 int tens = rs5c313_read_reg(sc, RS5C313_ ## y ## 10); \
189 dt->dt_wday = rs5c313_read_reg(sc, RS5C313_WDAY);
191 rtc_ce(sc, 0);
206 struct rs5c313_softc *sc = device_private(todr->todr_dev);
213 rtc_begin(sc);
215 rtc_ce(sc, 1);
217 rs5c313_write_reg(sc, RS5C313_CTRL, sc->sc_ctrl[0]);
218 if ((rs5c313_read_reg(sc, RS5C313_CTRL) & CTRL_BSY) == 0)
221 rtc_ce(sc, 0);
233 rs5c313_write_reg(sc, RS5C313_ ## x ## 1, t & 0x0f); \
234 rs5c313_write_reg(sc, RS5C313_ ## x ## 10, (t >> 4) & 0x0f); \
247 rs5c313_write_reg(sc, RS5C313_YEAR1, t & 0x0f);
248 rs5c313_write_reg(sc, RS5C313_YEAR10, (t >> 4) & 0x0f);
250 rs5c313_write_reg(sc, RS5C313_WDAY, dt->dt_wday);
252 rtc_ce(sc, 0);
255 sc->sc_valid = 1;
261 rs5c313_read_reg(struct rs5c313_softc *sc, int addr)
266 rtc_dir(sc, 1);
269 rtc_do(sc, 1); /* ignored */
270 rtc_do(sc, 1); /* R/#W = 1(READ) */
271 rtc_do(sc, 1); /* AD = 1 */
272 rtc_do(sc, 0); /* DT = 0 */
275 rtc_do(sc, addr & 0x8); /* A3 */
276 rtc_do(sc, addr & 0x4); /* A2 */
277 rtc_do(sc, addr & 0x2); /* A1 */
278 rtc_do(sc, addr & 0x1); /* A0 */
281 rtc_dir(sc, 0);
284 (void)rtc_di(sc);
285 (void)rtc_di(sc);
286 (void)rtc_di(sc);
287 (void)rtc_di(sc);
290 data = rtc_di(sc); /* D3 */
292 data |= rtc_di(sc); /* D2 */
294 data |= rtc_di(sc); /* D1 */
296 data |= rtc_di(sc); /* D0 */
303 rs5c313_write_reg(struct rs5c313_softc *sc, int addr, int data)
307 rtc_dir(sc, 1);
310 rtc_do(sc, 1); /* ignored */
311 rtc_do(sc, 0); /* R/#W = 0 (WRITE) */
312 rtc_do(sc, 1); /* AD = 1 */
313 rtc_do(sc, 0); /* DT = 0 */
316 rtc_do(sc, addr & 0x8); /* A3 */
317 rtc_do(sc, addr & 0x4); /* A2 */
318 rtc_do(sc, addr & 0x2); /* A1 */
319 rtc_do(sc, addr & 0x1); /* A0 */
322 rtc_do(sc, 1); /* ignored */
323 rtc_do(sc, 0); /* R/#W = 0(WRITE) */
324 rtc_do(sc, 0); /* AD = 0 */
325 rtc_do(sc, 1); /* DT = 1 */
328 rtc_do(sc, data & 0x8); /* D3 */
329 rtc_do(sc, data & 0x4); /* D2 */
330 rtc_do(sc, data & 0x2); /* D1 */
331 rtc_do(sc, data & 0x1); /* D0 */
Indexes created Mon Oct 27 17:09:47 GMT 2025