Cross Reference: /src/sys/dev/ic/rt2661.c

Lines Matching defs:txq
237 	error = rt2661_alloc_tx_ring(sc, &sc->txq[0], RT2661_TX_RING_COUNT);
243 	error = rt2661_alloc_tx_ring(sc, &sc->txq[1], RT2661_TX_RING_COUNT);
249 	error = rt2661_alloc_tx_ring(sc, &sc->txq[2], RT2661_TX_RING_COUNT);
255 	error = rt2661_alloc_tx_ring(sc, &sc->txq[3], RT2661_TX_RING_COUNT);
372 fail5:	rt2661_free_tx_ring(sc, &sc->txq[3]);
373 fail4:	rt2661_free_tx_ring(sc, &sc->txq[2]);
374 fail3:	rt2661_free_tx_ring(sc, &sc->txq[1]);
375 fail2:	rt2661_free_tx_ring(sc, &sc->txq[0]);
395 	rt2661_free_tx_ring(sc, &sc->txq[0]);
396 	rt2661_free_tx_ring(sc, &sc->txq[1]);
397 	rt2661_free_tx_ring(sc, &sc->txq[2]);
398 	rt2661_free_tx_ring(sc, &sc->txq[3]);
909 	struct rt2661_tx_ring *txq;
924 		txq = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq;
927 		data = &txq->data[txq->stat];
963 		DPRINTFN(15, ("tx done q=%d idx=%u\n", qid, txq->stat));
965 		txq->queued--;
966 		if (++txq->stat >= txq->count)	/* faster than % count */
967 			txq->stat = 0;
978 rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq)
984 		desc = &txq->desc[txq->next];
985 		data = &txq->data[txq->next];
987 		bus_dmamap_sync(sc->sc_dmat, txq->map,
988 		    txq->next * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE,
1005 		bus_dmamap_sync(sc->sc_dmat, txq->map,
1006 		    txq->next * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE,
1009 		DPRINTFN(15, ("tx dma done q=%p idx=%u\n", txq, txq->next));
1011 		if (++txq->next >= txq->count)	/* faster than % count */
1012 			txq->next = 0;
1275 			rt2661_tx_dma_intr(sc, &sc->txq[0]);
1278 			rt2661_tx_dma_intr(sc, &sc->txq[1]);
1281 			rt2661_tx_dma_intr(sc, &sc->txq[2]);
1284 			rt2661_tx_dma_intr(sc, &sc->txq[3]);
1612 	struct rt2661_tx_ring *txq = &sc->txq[ac];
1684 		desc = &txq->desc[txq->cur];
1685 		data = &txq->data[txq->cur];
1708 		bus_dmamap_sync(sc->sc_dmat, txq->map,
1709 		    txq->cur * RT2661_TX_DESC_SIZE, RT2661_TX_DESC_SIZE,
1712 		txq->queued++;
1713 		txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT;
1718 	data = &txq->data[txq->cur];
1719 	desc = &txq->desc[txq->cur];
1792 	bus_dmamap_sync(sc->sc_dmat, txq->map, txq->cur * RT2661_TX_DESC_SIZE,
1796 	    m0->m_pkthdr.len, txq->cur, rate));
1799 	txq->queued++;
1800 	txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT;
1844 			if (sc->txq[0].queued >= RT2661_TX_RING_COUNT - 1) {
2619 	RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr);
2620 	RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr);
2621 	RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr);
2622 	RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr);
2768 	rt2661_reset_tx_ring(sc, &sc->txq[0]);
2769 	rt2661_reset_tx_ring(sc, &sc->txq[1]);
2770 	rt2661_reset_tx_ring(sc, &sc->txq[2]);
2771 	rt2661_reset_tx_ring(sc, &sc->txq[3]);
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