Cross Reference: /src/sys/dev/ic/rt2661.c

Lines Matching refs:RAL_WRITE
798 			RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff);
1205 	RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16);
1207 	RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7);
1208 	RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18);
1209 	RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20);
1219 	RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff);
1232 		RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f);
1233 		RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff);
1244 	RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f);
1245 	RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff);
1265 		RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1);
1266 		RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2);
1300 	RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10);
1301 	RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0);
1571 	RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT);
1801 	RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1);
2005 	RAL_WRITE(sc, RT2661_PHY_CSR3, tmp);
2027 	RAL_WRITE(sc, RT2661_PHY_CSR3, val);
2057 	RAL_WRITE(sc, RT2661_PHY_CSR4, tmp);
2071 	RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR,
2074 	RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd);
2092 	RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
2098 	RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
2118 	RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp);
2132 	RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp);
2159 	RAL_WRITE(sc, RT2661_TXRX_CSR5, mask);
2209 	RAL_WRITE(sc, RT2661_PHY_CSR0, tmp);
2296 	RAL_WRITE(sc, RT2661_MAC_CSR4, tmp);
2299 	RAL_WRITE(sc, RT2661_MAC_CSR5, tmp);
2308 	RAL_WRITE(sc, RT2661_MAC_CSR2, tmp);
2311 	RAL_WRITE(sc, RT2661_MAC_CSR3, tmp);
2326 	RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
2348 	RAL_WRITE(sc, RT2661_AC_TXOP_CSR0,
2351 	RAL_WRITE(sc, RT2661_AC_TXOP_CSR1,
2356 	RAL_WRITE(sc, RT2661_CWMIN_CSR,
2363 	RAL_WRITE(sc, RT2661_CWMAX_CSR,
2370 	RAL_WRITE(sc, RT2661_AIFSN_CSR,
2408 	RAL_WRITE(sc, RT2661_MAC_CSR9, tmp);
2619 	RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr);
2620 	RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr);
2621 	RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr);
2622 	RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr);
2625 	RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr);
2628 	RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr);
2631 	RAL_WRITE(sc, RT2661_TX_RING_CSR0,
2637 	RAL_WRITE(sc, RT2661_TX_RING_CSR1,
2643 	RAL_WRITE(sc, RT2661_RX_RING_CSR,
2649 	RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa);
2652 	RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f);
2655 	RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2);
2659 		RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val);
2665 	RAL_WRITE(sc, RT2661_MAC_CSR1, 3);
2666 	RAL_WRITE(sc, RT2661_MAC_CSR1, 0);
2704 	RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
2710 	RAL_WRITE(sc, RT2661_MAC_CSR1, 4);
2713 	RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff);
2716 	RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10);
2717 	RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0);
2720 	RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1);
2749 	RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16);
2753 	RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
2756 	RAL_WRITE(sc, RT2661_MAC_CSR1, 3);
2757 	RAL_WRITE(sc, RT2661_MAC_CSR1, 0);
2760 	RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f);
2761 	RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff);
2764 	RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff);
2765 	RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff);
2790 	RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET);
2793 	RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0);
2794 	RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff);
2795 	RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0);
2798 	RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL);
2800 	RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET);
2803 	RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0);
2892 	RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX);
2914 	RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp);
3003 		RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8);
3017 	RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp);
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