Cross Reference: /src/sys/dev/ic/rtl81x9.c

Lines Matching defs:txd
622 	struct rtk_tx_desc *txd;
685 		txd = &sc->rtk_tx_descs[i];
688 		    &txd->txd_dmamap)) != 0) {
694 		txd->txd_txaddr = RTK_TXADDR0 + (i * 4);
695 		txd->txd_txstat = RTK_TXSTAT0 + (i * 4);
755 		txd = &sc->rtk_tx_descs[i];
756 		if (txd->txd_dmamap != NULL)
757 			bus_dmamap_destroy(sc->sc_dmat, txd->txd_dmamap);
776 	struct rtk_tx_desc *txd;
779 	while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL)
781 	while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_free)) != NULL)
785 		txd = &sc->rtk_tx_descs[i];
786 		CSR_WRITE_4(sc, txd->txd_txaddr, 0);
787 		SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_free, txd, txd_q);
817 	struct rtk_tx_desc *txd;
841 		txd = &sc->rtk_tx_descs[i];
842 		if (txd->txd_dmamap != NULL)
843 			bus_dmamap_destroy(sc->sc_dmat, txd->txd_dmamap);
1097 	struct rtk_tx_desc *txd;
1106 	while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL) {
1107 		txstat = CSR_READ_4(sc, txd->txd_txstat);
1114 		bus_dmamap_sync(sc->sc_dmat, txd->txd_dmamap, 0,
1115 		    txd->txd_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1116 		bus_dmamap_unload(sc->sc_dmat, txd->txd_dmamap);
1117 		m_freem(txd->txd_mbuf);
1118 		txd->txd_mbuf = NULL;
1153 		SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_free, txd, txd_q);
1231 	struct rtk_tx_desc *txd;
1237 	while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_free)) != NULL) {
1252 		    bus_dmamap_load_mbuf(sc->sc_dmat, txd->txd_dmamap,
1283 			    txd->txd_dmamap, m_new,
1302 		txd->txd_mbuf = m_head;
1305 		SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_dirty, txd, txd_q);
1311 		    txd->txd_dmamap, 0, txd->txd_dmamap->dm_mapsize,
1314 		len = txd->txd_dmamap->dm_segs[0].ds_len;
1316 		CSR_WRITE_4(sc, txd->txd_txaddr,
1317 		    txd->txd_dmamap->dm_segs[0].ds_addr);
1318 		CSR_WRITE_4(sc, txd->txd_txstat,
1484 	struct rtk_tx_desc *txd;
1496 	while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL) {
1498 		bus_dmamap_unload(sc->sc_dmat, txd->txd_dmamap);
1499 		m_freem(txd->txd_mbuf);
1500 		txd->txd_mbuf = NULL;
1501 		CSR_WRITE_4(sc, txd->txd_txaddr, 0);
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