Lines Matching refs:bus_space_read_2
244 tmp = bus_space_read_2(bst, bsh, BANK_SELECT_REG_W);
256 tmp = bus_space_read_2(bst, bsh, REVISION_REG_W);
270 mult = MCR_MEM_MULT(bus_space_read_2(bst, bsh, MEM_CFG_REG_W));
278 memsize = bus_space_read_2(bst, bsh, MEM_INFO_REG_W) & MIR_TOTAL_MASK;
291 tmp = bus_space_read_2(bst, bsh, IAR_ADDR0_REG_W + i);
326 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W);
427 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W);
469 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W);
523 tmp = bus_space_read_2(bst, bsh, MMU_CMD_REG_W);
774 if (bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) & FIFO_REMPTY)
873 v = bus_space_read_2(bst, bsh, INTR_STAT_REG_B);
926 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) &
945 tx_status = bus_space_read_2(bst, bsh, DATA_REG_W);
976 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY)
995 card_stats = bus_space_read_2(bst, bsh, COUNTER_REG_W);
1066 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W);
1182 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY)
1406 return bus_space_read_2(sc->sc_bst, sc->sc_bsh, MGMT_REG_W);
1459 mctl = bus_space_read_2(bst, bsh, TXMIT_CONTROL_REG_W);
Indexes created Tue Oct 28 02:10:10 GMT 2025