Cross Reference: /src/sys/dev/ic/spdmem.c

Lines Matching defs:cycle_time
496 		  int dimm_size, int cycle_time, int d_clk, int bits,
514 	if (cycle_time == 0) {
522 	 * cycle_time of 1.5ns displayed as PC3-10666.
530 		p_clk = (d_clk * bits) / 8 / cycle_time;
531 	d_clk = ((d_clk + cycle_time / 2) ) / cycle_time;
600 	int dimm_size, cycle_time, bits, tAA, i, speed, freq;
615 	cycle_time = s->sm_sdr.sdr_cycle_whole * 1000 +
633 		if (cycle_time < 8000)
642 	decode_size_speed(self, node, dimm_size, cycle_time, 1, bits, FALSE,
648 	    s->sm_sdr.sdr_banks_per_chip, cycle_time/1000,
649 	    (cycle_time % 1000) / 100);
665 	int dimm_size, cycle_time, bits, tAA, i;
680 	cycle_time = s->sm_ddr.ddr_cycle_whole * 1000 +
685 	decode_size_speed(self, node, dimm_size, cycle_time, 2, bits, TRUE,
691 	    s->sm_ddr.ddr_banks_per_chip, cycle_time/1000,
692 	    (cycle_time % 1000 + 50) / 100);
701 		((scale * s->sm_ddr.field + cycle_time - 1) / cycle_time)
714 	int dimm_size, cycle_time, bits, tAA, i;
730 	cycle_time = s->sm_ddr2.ddr2_cycle_whole * 1000 +
735 	decode_size_speed(self, node, dimm_size, cycle_time, 2, bits, TRUE,
742 	    cycle_time / 1000, (cycle_time % 1000 + 5) /10 );
750 		((scale * s->sm_ddr2.field + cycle_time - 1) / cycle_time)
796 	int dimm_size, cycle_time, bits;
823 	cycle_time = __DDR3_VALUE_PICO(s, tCKmin);
825 	decode_size_speed(self, node, dimm_size, cycle_time, 2, bits, FALSE,
834 	    cycle_time/1000, cycle_time % 1000);
837 	((val / cycle_time) + ((val % cycle_time) ? 1 : 0))
866 	int dimm_size, cycle_time, bits;
879 	cycle_time = (1000 * s->sm_fbd.fbdimm_mtb_dividend +
883 	decode_size_speed(self, node, dimm_size, cycle_time, 2, bits, TRUE,
890 	    cycle_time / 1000, (cycle_time % 1000 + 5) /10 );
907 	int dimm_size, cycle_time, ranks;
970 	cycle_time = __DDR4_VALUE(tCKAVGmin);
971 	decode_size_speed(self, node, dimm_size, cycle_time, 2,
985 	    cycle_time / 1000, cycle_time % 1000);
987 	tAA_clocks =  __DDR4_VALUE(tAAmin)  * 1000 / cycle_time;
988 	tRCD_clocks = __DDR4_VALUE(tRCDmin) * 1000 / cycle_time;
989 	tRP_clocks =  __DDR4_VALUE(tRPmin)  * 1000 / cycle_time;
991 		       s->sm_ddr4.ddr4_tRASmin_lsb) * 125 * 1000 / cycle_time;
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