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Lines Matching refs:sm_ddr4

406 		    s->sm_ddr4.ddr4_mod_type <
408 			type = spdmem_ddr4_module_types[s->sm_ddr4.ddr4_mod_type];
419 		if ((s->sm_ddr4.ddr4_hybrid)
420 		    && (s->sm_ddr4.ddr4_hybrid_media == 1))
911 	print_part(s->sm_ddr4.ddr4_part_number,
912 	    sizeof(s->sm_ddr4.ddr4_part_number));
914 	if (s->sm_ddr4.ddr4_mod_type < __arraycount(spdmem_ddr4_module_types))
916 		    spdmem_ddr4_module_types[s->sm_ddr4.ddr4_mod_type]);
918 		(s->sm_ddr4.ddr4_bus_width_extension) ? "" : "no ",
919 		(s->sm_ddr4.ddr4_has_therm_sensor) ? "" : "no ");
934 	dimm_size = (s->sm_ddr4.ddr4_capacity + 28)	/* chip_capacity */
937 		     + (s->sm_ddr4.ddr4_primary_bus_width + 3); /* bus width */
938 	switch (s->sm_ddr4.ddr4_device_width) {		/* DRAM width */
952 		    (s->sm_ddr4.ddr4_package_ranks + 1); /* log.ranks/DIMM */
953 		if (s->sm_ddr4.ddr4_signal_loading == 2) {
954 			dimm_size *= (s->sm_ddr4.ddr4_diecount + 1);
962 #define	__DDR4_VALUE(field) ((s->sm_ddr4.ddr4_##field##_mtb * 125 +	\
963 			     s->sm_ddr4.ddr4_##field##_ftb) - 		\
964 			    ((s->sm_ddr4.ddr4_##field##_ftb > 127)?256:0))
972 			  1 << (s->sm_ddr4.ddr4_primary_bus_width + 3),
975 	ranks = s->sm_ddr4.ddr4_package_ranks + 1;
978 	    s->sm_ddr4.ddr4_rows + 12, s->sm_ddr4.ddr4_cols + 9,
979 	    ranks, (ranks > 1) ? ((s->sm_ddr4.ddr4_rank_mix == 1)
981 	    1 << (2 + s->sm_ddr4.ddr4_logbanks),
982 	    1 << s->sm_ddr4.ddr4_bankgroups);
990 	tRAS_clocks = (s->sm_ddr4.ddr4_tRASmin_msb * 256 +
991 		       s->sm_ddr4.ddr4_tRASmin_lsb) * 125 * 1000 / cycle_time;